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BigB's avatar
BigB
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3 years ago

Reset on execution of bare-metal app after bootloader - DE10-Nano (Cyclone V)

Hardware: DE10-Nano demo board (Cyclone V) IDE: Arm DS 2022.0 SoC EDS: 20.1 (Standard) I'm developing a bare metal application for a Cyclone V. I am able to debug directly with no problems when u...
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Brett


I see that you are running on the branch 2022.04.

Could you try out the branch for 2022.01?

2022.01 is the latest stable branch release.


Regards

Jingyang, Teh


  • BigB's avatar
    BigB
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thank you for the idea to try. Unfortunately, I am getting the same result using the 2022.01 branch.

    U-Boot 2022.01-19547-g2544e805ea-dirty (Nov 10 2022 - 11:58:27 -0600)

    CPU: Altera SoCFPGA Platform
    FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
    BOOT: SD/MMC Internal Transceiver (3.0V)
    Watchdog enabled
    DRAM: 1 GiB
    MMC: dwmmc0@ff704000: 0
    Loading Environment from MMC... *** Warning - bad CRC, using default environment

    In: serial
    Out: serial
    Err: serial
    Model: Altera SOCFPGA Cyclone V SoC Development Kit
    Net:
    Warning: ethernet@ff702000 (eth0) using random MAC address - 72:71:f8:f1:63:8e
    eth0: ethernet@ff702000
    Hit any key to stop autoboot: 0
    => undefined instruction
    pc : [<02000bae>] lr : [<0200005f>]
    reloc pc : [<c309cbee>] lr : [<c309c09f>]
    sp : 03ffffe8 ip : 3ffe4248 fp : 02000bf8
    r10: 02000bf8 r9 : 3bf61ed0 r8 : 00000000
    r7 : 02000be7 r6 : 00000000 r5 : 00000000 r4 : 00000000
    r3 : 00000000 r2 : 80000000 r1 : 02000d60 r0 : 02000c08
    Flags: nZCv IRQs off FIQs off Mode SVC_32 (T)
    Code: b2c0 1c53 604b 7010 (4770) eef1
    Resetting CPU ...

    resetting ...

    Thanks,
    Brett