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Silvan's avatar
Silvan
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Interrup numbers of Arria 10 EDAC

Hi, I try to enable the Error Detection and Correction (EDAC) for EMAC1 on my Arria 10 SoC device. I found the device tree entries for EMAC0 in the Linux kernel sources: emac0-rx-ecc@ff8c0800 { ...
Arm Processor
Sw Development
Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
4 months ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.