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dpeng's avatar
dpeng
Icon for New Contributor rankNew Contributor
4 months ago
Solved

enable bridge crashes Linux

Hi, We selected a Cyclone V SoC FPGA for our project. I started on Terasic demo boards (DE0 and ADC-SoC). On these boards, that both bear a Cyclone V (P/N 5CSEMA4U23C6N), I could, with a devicetree ...
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  • dpeng's avatar
    dpeng
    3 months ago

    So, I think I made some progress.

    1. I enable the bridges in Barebox by setting the status and bridge-enable properties.
    2. In the Linux devicetree overlay, I only set the status property, not the bridge-enable property.

    The Barebox DT (the "0x1" syntax matters, it seems):

    &fpga_bridge0 {
	status = "okay";
	bridge-enable = <0x1>;
};

    The Linux DT overlay:

    /dts-v1/;
/plugin/;

/ {
	fragment@0 {
		target = <&base_fpga_region>;

		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			// The .rbf file must be placed in /lib/firmware
			firmware-name = "soc_firwmare.rbf";
			fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
		};
	};

	/* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */
	fragment@1 {
		target = <&fpga_bridge0>;

		__overlay__ {
			status = "okay";
			// Don't set bridge-enable!
			// bridge-enable = <1>;
		};
	};

	/* Enable the HPS to FPGA bridge (hps2fpga) */
	fragment@2 {
		target = <&fpga_bridge1>;

		__overlay__ {
			status = "okay";
			// Don't set bridge-enable!
			// bridge-enable = <1>;
		};
	};
};

    Then, I when I check the status of the bridges, I get what I expect:

    # for f in /proc/device-tree/soc/fpga?bridge*; do echo $(basename $f)":" $(cat $f/status); done
fpga-bridge@ff600000: disabled
fpga-bridge@ffc25080: disabled
fpga_bridge@ff400000: okay
fpga_bridge@ff500000: okay
#

    I didn't try to communicate between the HPS and the FPGA yet, but it looks promising.

JitLoonL_Altera's avatar
JitLoonL_Altera
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hi @dpeng ,

Looking at your DT, the bridges are currently disabled, which explains why changing the clock in Linux DT alone didn’t help.

For your setup:

  • fpga_bridge@ff400000 (LW HPS-to-FPGA) is the one you likely need for HPS → FPGA communication. You should enable it in your DT like this:

&fpga_bridge0 {
status = "okay";
clocks = <&h2f_user2_clk>; /* match Platform Designer */
resets = <0x06 0x61>; /* keep original reset lines */
};

  • fpga-bridge@ffc25080 (FPGA-to-SDRAM) only needs enabling if your design specifically requires FPGA → SDRAM access.

Remember, the DT in Barebox should match the Platform Designer settings. Enabling the bridge and assigning the correct clock there is necessary before Linux can use it.

After this change, check the live DT in Linux - status should now be okay and the bridge should be functional.

  • dpeng's avatar
    dpeng
    Icon for New Contributor rankNew Contributor
    4 months ago

    I am not able to dump the live tree after I apply the overlay that enables the bridge, because the system freezes totally at this step. This is precisely what I'm trying to fix.

    In the project, i.e. the Mercury+ SA2 ST1 Reference Design, the Platform Designer setup looks like this:

    I checked that the handoff files in Barebox are up to date with the design. In the Barebox DT, I added these lines, just like in the Linux DT:

    &fpga_bridge0 {
	clocks = <&h2f_user2_clk>;
};

    I confirmed that the clock is changed by dumping the live tree and before applying the overlay.

    I'm trying to enable the bridge in a Linux overlay:

    	fragment@1 {
		target = <&fpga_bridge0>;

		__overlay__ {
			status = "okay";
			bridge-enable = <1>;
		};
	};

    But applying the overlay keeps freezing the system.