Contributor
Solved: bring MAC signals up a module
Occasional ContributorHello K606
As you wait for the sof file analysis to come back, you can check the below information that one of my colleague shared
For a MAC-to-MAC loopback test, it requires additional logic. The main logic that enables this is:
fyi, this code above has not gone thru validation, but my colleague has tested the basic functionalities (ping and iperf transfers).
The DTSI is correct.
But additional kernel option (network namespace) needs to be enabled to ensure the data transfer is not virtual. This is because Linux network stack is pretty intelligent to detect transfer between interfaces on the same host and will attempt SW transfers without going thru MAC.
Thanks
ContributorThanks @Sparrow_Altera!
Would you mind expanding on the 'additional kernel option (network namespace)'? Would it just be a case of adding
CONFIG_NET_NS=y
To the .config?
I also had a look at the snippet you shared, adapting it to my project as followed:
module dual_emac_interface ( // EMAC0 Signals output wire emac0_mac_tx_clk_o_wire, // clock out for tx (not used in 10/100 Mbps) input wire emac0_mac_tx_clk_i_wire, // clock in for tx (not used in 1/2.5 Gbps, but fed signal either way - should be 25MHz) input wire emac0_mac_rx_clk_wire, // clock for rx path output wire emac0_mac_rst_tx_n_wire, // reset for tx path output wire emac0_mac_rst_rx_n_wire, // reset for rx path output wire emac0_mac_txen_wire, // transmit enable signal output wire emac0_mac_txer_wire, // transmit error signal input wire emac0_mac_rxdv_wire, // receive data valid signal input wire emac0_mac_rxer_wire, // receive error signal input wire [7:0] emac0_mac_rxd_wire, // for 10/100 Mbps designs, only bits [3:0] are used input wire emac0_mac_col_wire, // collision signal (half-duplex only) input wire emac0_mac_crs_wire, // carrier sense signal (half-duplex only) output wire [2:0] emac0_mac_speed_wire, // set to 3'b011 for 1 Gbps (125 MHz) output wire [7:0] emac0_mac_txd_o_wire, // for 10/100 Mbps designs, only bits [3:0] are used // EMAC1 Signals output wire emac1_mac_tx_clk_o_wire, input wire emac1_mac_tx_clk_i_wire, input wire emac1_mac_rx_clk_wire, output wire emac1_mac_rst_tx_n_wire, output wire emac1_mac_rst_rx_n_wire, output wire emac1_mac_txen_wire, output wire emac1_mac_txer_wire, input wire emac1_mac_rxdv_wire, input wire emac1_mac_rxer_wire, input wire [7:0] emac1_mac_rxd_wire, input wire emac1_mac_col_wire, input wire emac1_mac_crs_wire, output wire [2:0] emac1_mac_speed_wire, output wire [7:0] emac1_mac_txd_o_wire ); reg emac0_mac_tx_clk_i_reg, emac0_mac_rxer_reg, emac0_mac_rxdv_reg; reg [7:0] emac0_mac_rxd_reg; reg emac1_mac_tx_clk_i_reg, emac1_mac_rxer_reg, emac1_mac_rxdv_reg; reg [7:0] emac1_mac_rxd_reg; assign emac1_mac_tx_clk_i_wire = emac0_mac_tx_clk_o_wire; assign emac1_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire; assign emac1_mac_rxdv_wire = emac1_mac_rxdv_reg; assign emac1_mac_rxer_wire = emac0_mac_txer_wire; assign emac1_mac_rxd_wire = emac1_mac_rxd_reg; assign emac1_mac_col_wire = 1'b0; assign emac1_mac_crs_wire = 1'b1; assign emac1_mac_speed_wire = 3'b011; assign emac0_mac_tx_clk_i_wire = emac1_mac_tx_clk_o_wire; assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire; assign emac0_mac_rxdv_wire = emac0_mac_rxdv_reg; assign emac0_mac_rxer_wire = emac1_mac_txer_wire; assign emac0_mac_rxd_wire = emac0_mac_rxd_reg; assign emac0_mac_col_wire = 1'b0; assign emac0_mac_crs_wire = 1'b1; assign emac0_mac_speed_wire = 3'b011; always @ (posedge emac1_mac_tx_clk_o_wire) begin if(!emac1_mac_rst_tx_n_wire) begin emac0_mac_rxdv_reg <= 1'b0; emac0_mac_rxd_reg <= 8'b0; end else begin emac0_mac_rxdv_reg <= emac1_mac_txen_wire; emac0_mac_rxd_reg <= emac1_mac_txd_o_wire; end end always @ (posedge emac0_mac_tx_clk_o_wire) begin if(!emac0_mac_rst_tx_n_wire) begin emac1_mac_rxdv_reg <= 1'b0; emac1_mac_rxd_reg <= 8'b0; end else begin emac1_mac_rxdv_reg <= emac0_mac_txen_wire; emac1_mac_rxd_reg <= emac0_mac_txd_o_wire; end end endmodule
I again found the same initialisation error as here
With the emac clock tree as followed:
$ cat /sys/kernel/debug/clk/clk_summary | grep emac root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep emac emaca_free_clk 1 1 0 250000000 0 0 50000 Y emac2_clk 1 1 0 250000000 0 0 50000 Y emac1_clk 0 0 0 250000000 0 0 50000 Y emac0_clk 0 0 0 250000000 0 0 50000 Y emac_ptp_free_clk 1 1 0 400000000 0 0 50000 Y emac_ptp_clk 1 1 0 400000000 0 0 50000 Y i2c_emac2_pclk 0 0 0 100000000 0 0 50000 Y i2c_emac1_pclk 0 0 0 100000000 0 0 50000 Y i2c_emac0_pclk 0 0 0 100000000 0 0 50000 Y emacb_free_clk 0 0 0 70000000 0 0 50000 Y
Many thanks,
K
