Sparrow_Altera
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Re: Agilex 5 EMAC to EMAC : Driver error
Hello K606 As you wait for the sof file analysis to come back, you can check the below information that one of my colleague shared For a MAC-to-MAC loopback test, it requires additional logic. The main logic that enables this is: fyi, this code above has not gone thru validation, but my colleague has tested the basic functionalities (ping and iperf transfers). The DTSI is correct. But additional kernel option (network namespace) needs to be enabled to ensure the data transfer is not virtual. This is because Linux network stack is pretty intelligent to detect transfer between interfaces on the same host and will attempt SW transfers without going thru MAC. ThanksRe: max10 remote system update nios with uart
Hello Nios II is EOL, Altera stop selling Nios II/f license. New users need to migrate to Nios V and apply the Nios V license. Regarding the example design, couple of points below that can help you. To simplify the design, it can be divided into three function blocks: RSU block (Dual Configuration IP to handle RSU) UART block (Communication thru UART) Booting block (Nios to boot from QSPI) RSU block (Dual Configuration IP to handle RSU) UART block (Communication thru UART, such as printf & scanf) Booting block (Nios booting from QSPI) Below User Guides will help you to understand more about these function blocks. RSU block (Dual Configuration IP to handle RSU) MAX® 10 FPGA Configuration User Guide (How does Dual Configuration IP handle Max 10 RSU?) MAX® 10 User Flash Memory User Guide (Dual Configuration IP switches the target CFM only, you will need On-Chip Flash IP to change the FPGA Image in CFM) UART block (Communication thru UART) UART Core (Altera HAL driver to send/receive UART data in Software Programming Model subchapter) Booting block (Nios booting from QSPI) Nios® II Processor Booting from QSPI Flash (QSPI Controller + OCRAM is a must to boot Nios II from QSPI) Nios® V Processor Booting from General Purpose QSPI Flash (QSPI Controller + OCRAM is a must to boot Nios V from QSPI) And finally connecting the 3 logic blocks to get the whole design, ThanksRe: max10 remote system update nios with uart
Hello Can you check your design settings in Quartus with the example design settings, the link below provides the file for the example that you are trying to follow Intel® MAX® 10 FPGA – Intel MAX 10 FPGA Remote System Upgrade (RSU) over UART for the Nios® II Processor Design Example Thanks
