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aiedb's avatar
aiedb
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7 months ago

max10 remote system update nios with uart

hii i am trying to follow the application note to build a system to do a remote update of max10 over uart with nios 2 i built the qsys system with the on chip flash in order to store a factory an...
Fpga Devkit
aiedb's avatar
aiedb
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

hii when i compile this project i get errors due to licince issues how can i solve it ?

Sparrow_Altera's avatar
Sparrow_Altera
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

Hello

Nios II is EOL, Altera stop selling Nios II/f license.

New users need to migrate to Nios V and apply the Nios V license.

Regarding the example design, couple of points below that can help you.

To simplify the design, it can be divided into three function blocks:

  • RSU block (Dual Configuration IP to handle RSU)
  • UART block (Communication thru UART)
  • Booting block (Nios to boot from QSPI)

RSU block (Dual Configuration IP to handle RSU)

UART block (Communication thru UART, such as printf & scanf)

Booting block (Nios booting from QSPI)

Below User Guides will help you to understand more about these function blocks.

RSU block (Dual Configuration IP to handle RSU)

UART block (Communication thru UART)

  • UART Core (Altera HAL driver to send/receive UART data in Software Programming Model subchapter)

Booting block (Nios booting from QSPI)

And finally connecting the 3 logic blocks to get the whole design,

Thanks

  • aiedb's avatar
    aiedb
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    hii thanks a lot for reply that helped me alot now i understand what is the problem

    • Sparrow_Altera's avatar
      Sparrow_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      That's great, glad that helped.

      Thanks

  • aiedb's avatar
    aiedb
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    hii

    do you have a design guide that explains how to do RSU without the need of a nios 2 processor

    lets say i want to write my own vhdl code to perform the rsu , from what i understand

    1- i need to be able to read and write the cfm sections in order to write the my image into cfm0 and cfm1/2 in dual compressed mode

    2- trigger the fpga in order to read the new image from cfm1/2 and configure the fpga logic by hardware or software

    i would like to know if there an application note that explains how to do RSU manually without the help of nios

    3- another question if i configure the nios v processor to boot from qspi does it take up from the logic elements ?

    • SueC_Altera's avatar
      SueC_Altera
      Icon for Contributor rankContributor
      7 months ago

      Hi Aiedb,

      It is helpful to start a new thread for new questions.

      I hope you have read the Max10 configuration user guide - it has a detailed RSU section.

      Sue

    • Sparrow_Altera's avatar
      Sparrow_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      Hello

      Please open a new thread for this item as this is a new topic.

      Thanks