Preloader uboot SPL

Hi,

We have a custom Cyclone V board that runs vxWorks. All boot images are coming from the QSPI with preloader separated from uboot. Preloader starts @ 0x0 location, u-boot @ 0x60000.

I'm not trying to have Linux work on this board but i'm currently stuck with making the pre-loader and u-boot to work. I followed the instructions from Rocketboards for (Cycone V Soc - Boot from QSPI) using Ubuntu22.04 on a VM on how to generate the preloader and u-boot.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Introduction

I managed to compile/generate the u-boot-with-spl.sfp file using the socfpga_cyclone5_qspi_defconfig in the procedure, assuming that the generated file should at least show some boot messages on the serial port.

But at power up, our custom board isn't showing any boot messages on the serial port. Not even garbage text.

I then tried following the Mainline u-Boot for SocFPGA procedure to create a defconfig for our custom board but it's not compiling waiting for user input/decision.

https://www.rocketboards.org/foswiki/Documentation/MainlineUBootForSoCFPGA

So my questions are:

- can i just write the u-boot-with-spl.sfp directly to the QSPI? Considering the system already works with pre-loader and u-boot separated.

- is there a guide on how to generate a preloader and uboot for a custom board?

- for the custom defconfig, is there document that describes what each lines in the file mean?

I am currently enrolled to Intel® SoC FPGA Basics this coming May 25th. I'd appreciate if you can share new materials that can help me get familiarized with using embedded Linux on a Cyclone V system.

Thanks!

Jeet14
3 years ago
Hi Joel,

Thanks for attending teams call.
Let me know if you have any other query on this.

Regards
Tiwari

28 Replies

Jeet14
Frequent Contributor
3 years ago
Hi,

Please add below links in your socfpga_cyclone5.dtsi
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};

Regarding preloader for cyclone V, you need to use the bsp-editor from platform design. Please refer below links for creating custom preloader for cyclone V.
https://github.com/sahandKashani/SoC-FPGA-Design-Guide/blob/master/DE1_SoC/SoC-FPGA%20Design%20Guide/SoC-FPGA%20Design%20Guide%20%5BDE1-SoC%20Edition%5D.pdf
https://community.intel.com/t5/FPGA-Wiki/ASDF-Hands-On-SoC-Bare-Metal-Demo/ta-p/735146

Regards
Tiwari
Jeet14
Frequent Contributor
3 years ago
Hi,

Let me know if you have any query on this.

Regards
Tiwari
- JBayl
  Occasional Contributor
  3 years ago
  I still get 0MB RAM size.
  I edited the dtsi file before running the python script from this step:
  cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \ -o ../../../../board/altera/cyclone5-socdk/qts
  Note again that i'm not using the Cyclone V development board but our own custom board and FPGA source.
  Boot Log:
  U-Boot SPL 2022.10-24687-g61ae22e548-dirty (May 18 2023 - 15:13:00 +0100)
  DDR: Warning: DRAM size from device tree (1024 MiB)
  mismatch with hardware (0 MiB).
  DDR: Error: DRAM size from device tree is greater
  than hardware size.
JBayl
Occasional Contributor
3 years ago
Still working on it. I see that the socfpga_cyclone5.dtsi gets accessed when i run make uboot (got a syntax error initially and i got prompted about it). Fixed the syntax error but the resulting binaries aren't working. No boot log.
The 2 links you sent are still using the old method (bsp-editor), so i don't feel inclined to follow that at the moment since Rocketboard's procedure shows SoC EDS will be discontinued.
Jeet14
Frequent Contributor
3 years ago
Hi,

Any update on the issue.

Regards
Tiwari
JBayl
Occasional Contributor
3 years ago
Nope, i'm still stuck. Any updated procedure or reading materials or training suggestions from Intel?
Something similar to this link from Youtube but runs through the new steps?
https://www.youtube.com/watch?v=vS7pvefsbRM&t=245s
Jeet14
Frequent Contributor
3 years ago
Hi,

I am checking with engineering team on the latest tool user guide, training material if available I will update you ASAP.

Regards
Tiwari
JBayl
Occasional Contributor
3 years ago
Thanks Tiwari.
I attended the Intel SoC FPGA lecture. I was able to do the lab work but it wasn't clear to me how to execute the procedure for a custom board.
It looks like I'm missing a lot when executing these steps:
Configure and build U-Boot:
cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga export CROSS_COMPILE=arm-none-linux-gnueabihf- make socfpga_cyclone5_qspi_defconfig make -j 48
Do you have a tutorial on how to edit/copy/customize a _defconfig file?
What part of this sequence gets the files generated by cv_bsp_generator.py?
Thanks
Jeet14
Frequent Contributor
3 years ago
Hi,

Please try Step by step procedure given in below link for Cyclone V SoC- Boot from QSPI-
https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI

The only thing you need to take care is while generating your .sof file for your custom cyclone project & based on this you need to configure socfpga.dtsi & socfpga_cyclone5.dtsi

cv_bsp_generator.py script is used to take the sources from the handoff folder i.e. quartus hardware project, format them appropriately and copy them to the U-Boot source code

If still issue comes then I will setup a call on 1st June as next 2 days I am out of office.

Regards
Tiwari
Jeet14
Frequent Contributor
3 years ago
Hi,

Any update on the previous reply?

Regards
Jeetesh
JBayl
Occasional Contributor
3 years ago
No progress. I'm currently trying out the steps on my SoCKIT board, but no significant progress yet. How do we setup a call?

Forum Discussion

Preloader uboot SPL

28 Replies

Recent Discussions

F2SDRAM test inquiries.

Agilex 5E HPS and Linux

LWH2F Throughput

Reg SoC Example without using Linux

Reg Agilex5 A5ED028BM16AE5S SoC - USB3.0