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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Preloader uboot SPL

Hi, We have a custom Cyclone V board that runs vxWorks. All boot images are coming from the QSPI with preloader separated from uboot. Preloader starts @ 0x0 location, u-boot @ 0x60000. I'm not...
  • Jeet14's avatar
    Jeet14
    3 years ago

    Hi Joel,


    Thanks for attending teams call.

    Let me know if you have any other query on this.


    Regards

    Tiwari


Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Let me know if you have any query on this.


Regards

Tiwari


JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I still get 0MB RAM size.

I edited the dtsi file before running the python script from this step:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts

Note again that i'm not using the Cyclone V development board but our own custom board and FPGA source.

Boot Log:

U-Boot SPL 2022.10-24687-g61ae22e548-dirty (May 18 2023 - 15:13:00 +0100)
DDR: Warning: DRAM size from device tree (1024 MiB)
mismatch with hardware (0 MiB).
DDR: Error: DRAM size from device tree is greater
than hardware size.