New Contributor
Occasional ContributorHi Arun,
devmem2 is the most common and easiest way to access a FPGA bridge from Linux kernel, to do it another way, you could try adding a node similar to https://www.kernel.org/doc/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt into https://github.com/altera-fpga/linux-socfpga/blob/QPDS25.1_REL_GSRD_PR/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts, but with another values for register range, reset, and clock. You will also need a custom driver to access the node you created.
New ContributorHi AlanCLTan​,
We have followed the procedure as per the document and enabled all the drivers related to the bridge but the fpga_bridge directory is still empty. We have also attached our updated DTS.
New ContributorHi AlanCLTan​,
If anything else needs to be updated please let us know
New ContributorHi Arun,
On Agilex 5 you do not need those bridge entries in the device tree, and consequently you will not see corresponding folders in sysfs.
Please let me know what functionality you are missing, that you relied on the old sysfs bridge entries, and will investigate how to help you get it.
Once bridges are enabled, all you have to do to access that memory is to map it in a kernel driver, similar to how the devmem2 maps it from user space. It is how drivers access peripheral memory.
In case of FPGA configuration first, bridges can be enabled at any time. In case of HPS boots first, the bridges can be enabled only after the core fabric is configured.
Bridges can be enabled from U-Boot explicity (using 'bridge enable') or automatically (by the 'bootm' command, when it also configures the fabric). Bridges are also enabled automatically when the fabric is configured from Linux, through a device tree overlay.
We do not have an Agilex 5 example for configuring the fabric from Linux yet, but it is similar to the Agilex 7: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-7/f-series/soc/fabric-config/ug-linux-fabric-config-agx7f-soc/
Thank you,
Radu
New ContributorHi Rocketborg,
In U-Boot, we load and enable the bridge using the following commands:
fatload mmc 0:1 ${rbf_addr} ${rbffile}
fpga load 0 ${rbf_addr} ${filesize}
bridge enable 0x3
Similarly, we need to load the RBF from the kernel OS and access the bridge from within the kernel.without the use of devmem2 package
I will try to replicate the same in our DTS File
https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-7/f-series/soc/fabric-config/ug-linux-fabric-config-agx7f-soc/
Please let us know if any way is there
New ContributorHi Arun,
The information from that Agilex 7 page should enable you to configure the fabric from Linux, and also access the sysid from Linux, as an example IP. Accessing that IP is not done through devmem, but through its sysfs interface. In the future we will have similar Agilex 5 examples.
Once the fabric is configured, and bridges enabled, there is nothing special about the bridges, they are just memory windows, and IP happens to have its base address in that window.
Let me know if you have any further questions/issues.
Thank you,
Radu
Regular Contributor
Let me know if further assistance is needed or if the explanation answered your doubts.
Regards
tehjingy
Regular ContributorHi
As we do not hear back from you for sometime, we will transition this thread into community support onwards.
Regards
tehjingy
