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keshavp's avatar
keshavp
Icon for New Member rankNew Member
11 hours ago

NAND flash issue with dual-core ARM® Cortex®-A9

The 5CSEBA2U19I7SN SoC HPS NAND pins are connected to a 4Gb NAND flash memory chip (S34ML04G200TFI003). In this design, the active-low Write Protect pin (#WP) is connected to both a 10kΩ pull-up resistor (to 3.3V) and a 10kΩ pull-down resistor (to Ground). During booting or flashing, a few NAND flash chips do not work properly, and a few nand flashes have been permanently damaged. Is connecting the #WP pin to both a pull-up and a pull-down resistor a correct hardware approach for cyclone SOC HPS NAND configuration? 

Best Regards,

Keshav

 

 

 

Hps Boot

2 Replies

  • kbrunham_altera's avatar
    kbrunham_altera
    Icon for New Contributor rankNew Contributor
    8 hours ago

    Hi Keshav,

    This structure will have WP be ~1.65V since it will be between your 2 resistors. Did you use an existing board as the reference for this NAND interface?

  • ai_responder's avatar
    ai_responder
    Icon for Community Manager rankCommunity Manager
    10 hours ago

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