Forum Discussion
EricOpitz
Occasional Contributor
Occasional ContributorLWH2F Throughput
Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agi...
NDoe
New Contributor
New ContributorHi, we are also seeing similar issues with both the lwhps2fpga and hps2fpga interfaces.
The board is the Terasic DE25-Nano, the device is A5EB013BB23BE4SR1 with Quartus version 25.3.1 patch 1.02.
The bus cycle completes quickly in the time expected, but repeated bus cycles stall for a very long time between consecutive reads or consecutive writes. In my case I am seeing a delay of 400ns between cycle end and the next cycle start with all bus clocks connected to a single 100MHz source.
Best regards,
Nigel Doe
