LWH2F Throughput

Hi tehjingy_Altera​,

I took some measurements with the scope that I want to share with you.

I've modified the Agilex 5 QSYS image:
- In the "Avalon Memory Mapped Pipeline Bridge Inte FPGA IP" I've deactivated the options "Pipeline command signals" and "Pipeline response signals". This has improved performance slightly.
- I want to monitor the AXI signals directly. I have exported the AXI signals, output them on pins, and reimport them in QSYS using an AXI bridge. The bridge appears to add a small delay, degrading the performance slightly.

The read/write performance is:
read: 24.8 MB/s
write: 17.8 MB/s

Note that write is slightly slower compared to my first post.
Above performance measurements and the measurements from my first post were taken using the A76 (taskset -c 2). When I run the memory test on A55 (taskset -c 0) I get:
read: 16.3 MB/s
write: 17.8 MB/s
Surprisingly, the read performance is a lot worse compared to A76.

Attached you find corresponding scope images.
From the scope images you can see that the AXI write is finished (bvalid) in <50ns. The majority of the time is spent waiting for the next request from the CPU.

Do you see a similar behavior on your systems?

Kind Regards,
Eric Opitz

----

legend:
axi0 = agilex is master
axi1 = AXI-To-AvalonMM converter is master
mm_test = After the AXI-To-AvalonMM converter
D[ 0] = axi0_awvalid;
D[ 1] = axi1_awready;
D[ 2] = axi0_wvalid;
D[ 3] = axi0_wlast;
D[ 4] = axi1_wready;
D[ 6] = axi1_bvalid;
D[ 7] = axi0_bready;
D[ 8] = axi0_arvalid;
D[ 9] = axi1_arready;
D[10] = axi1_rvalid;
D[11] = axi0_rready;
D[12] = mm_test_write;
D[13] = mm_test_read;
D[14] = mm_test_readdatavalid;

Read CPU 0 (A55)

Read CPU 2 (A76)

Write CPU 0 (A55)

Write CPU 2 (A76)