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EricOpitz
Occasional Contributor
Occasional ContributorLWH2F Throughput
Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agi...
EricOpitzOccasional Contributor
Occasional ContributorOur FPGA design has the workaround activated already.
I've also tried deactivating it ("Override default cache size" = false). It did not degrade the performance in my particular case.
Kind Regards,
Eric Opitz
