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EricOpitz's avatar
EricOpitz
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

LWH2F Throughput

Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agi...
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EricOpitz's avatar
EricOpitz
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hi tehjingy_Altera​,

Yes our device is affected by the errata. The device number is A5ED013BB32AE4S. The errata suggests the workaround "Reduce L3 cache from 2MB to 1MB." We have configured this workaround in QSYS ("Override default cache size", MPU L3 Cache Size = 1MB). 

Should the workaround eliminate the performance issues entirely?

Kind Regards,
Eric Opitz

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi EricOpitz 

     

    This would not eliminate the performance issue but it would help improve the performance of the device.