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K606's avatar
K606
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1 year ago
Solved

Linux mSGDMA Driver Agilex 5

I am trying to use stream-to-memory DMA to move data. This is the design, showing the important Quartus connections:  Which corresponds to this address config: # address map write_sdram ...
Sw Development
Sw Library
  • StefanG_Altera's avatar
    StefanG_Altera
    1 year ago

    Hi,

    if you have a GHRD for your current board you can easily adapt the HW design (created for a supported board via e.g. build_hw_f2h_bridge.sh). The external periphery required on the demo designs is minimal (HPS-EMIF, HPS clock and UART).

wangduoyu's avatar
wangduoyu
Icon for New Contributor rankNew Contributor
7 months ago

Hello, I am also currently working on MSGDMA development. I have successfully established access to the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode, similar to yours.

I have two specific questions regarding the implementation:

1、Is configuring the standard Linux kernel driver a mandatory prerequisite for the MSGDMA to function correctly, or can it operate independently?

2、I noticed that you are writing to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM (FPGA-to-SDRAM) interface path, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?