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Silvan's avatar
Silvan
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Interrup numbers of Arria 10 EDAC

Hi, I try to enable the Error Detection and Correction (EDAC) for EMAC1 on my Arria 10 SoC device. I found the device tree entries for EMAC0 in the Linux kernel sources: emac0-rx-ecc@ff8c0800 { ...
Arm Processor
Sw Development
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hello Silvan,

Can you share with me the complete boot log? this will help me in debugging the boot procedure.

In the meantime, I will try to replicate the scenario with my dev kit for further debugging.

Thank you,

Fawaz.