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Silvan's avatar
Silvan
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Interrup numbers of Arria 10 EDAC

Hi, I try to enable the Error Detection and Correction (EDAC) for EMAC1 on my Arria 10 SoC device. I found the device tree entries for EMAC0 in the Linux kernel sources: emac0-rx-ecc@ff8c0800 { ...
Arm Processor
Sw Development
Silvan's avatar
Silvan
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Hi Sue

Thank you for the quick replay.

Then I do not understand the interrupts entry in the device tree blob, where interrupt 4, 36 for emac0 rx and 5, 37 for emac0 tx is declared.

Can you explain me the four numbers? And which are the valid configuration for EMAC1?

I see for all ECC entries in the device tree a configured interrupt number: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi?h=linux-6.6.y#n723

Where is the link of this numbers to the hardware? Or do I misunderstand something?

Are the numbers some how related with the System Manager? I mean, the documentation says that

"The ECC controller has the ability to generate single- and double-bit error interrupts to the System Manager."

see here: https://www.intel.com/content/www/us/en/docs/programmable/683711/22-3/ecc-controller-interrupts.html

Thank you,

Silvan