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aucamera1's avatar
aucamera1
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28 days ago

HPS f2sdram read/write errors

I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic.

I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus

on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic.

I can perform read and write cycles and everything flows correctly.  I get appropriate response from the f2sdram.

however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error.

i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. 

Anything common that I might have missed in my setup?

general

5 Replies

  • Nirav_Altera's avatar
    Nirav_Altera
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    27 days ago

    Hello aucamera1,

    One clarification: Are you running an FPGA-only design, or is the HPS also being booted (SPL/ATF/U-Boot) before you access F2SDRAM?


      • Yoda_Altera's avatar
        Yoda_Altera
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        23 days ago

        Hello aucamera1,

        I am Jeff, the Agilex 5 HPS / HPS-EMIF expert at Altera.

        1. How much DDR4 do you have attached to the HPS?   8GB?
        2. See the memory map at:  

          https://docs.altera.com/r/docs/814346/25.3.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/total-address-map-graphical

        3. The addresses from the FPGA perspective to SDRAM (F2SDRAM) (blue regions) are: 
          1. 0x00_8000_0000 - 0x01_0000_0000 (first 2 GB of DDR)
          2. 0x08_8000_0000 - 0x10_0000_0000 (next 30 GB of DDR)
          3. 0x88_0000_0000 - 0xFF_FFFF_FFFF (next 480 GB of DDR)
        4. So, please try read/write to somewhere in the range of DDR attached, such as 0x00_8000_0000 (which is really @ 0x0 of the attached DDR) or 0x08_8000_0000 (which is really @ 2GB of the attached DDR).
        5. BUT.... be careful because you could be "modifying" anything that is out in the HPS DDR, such as Linux OS, etc.
        6. Lastly, can you explain what you mean by:
          1. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus

         

        If the above does not work, then we need to focus on making sure the F2SDRAM bridge is properly open and there are no OS blocking issues and/or firewall issues.

        Regards,

        Jeff

  • aucamera1's avatar
    aucamera1
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    28 days ago

    I should also add, that even though the read/write operations otherwise execute successfully, the read back data is random and will change on every read even though its reading the same address.