New ContributorCurrently we are working with Agilex FPGA SOC Design.
First time am using this Agilex SOC Design,would like to create a QSYS Design by connecting FPGA and HPS Interfaces through Platform design tool.
Could you please provide any example design which has FPGA + HPS Connected to PCIe/Ethernet or any other interface connections.
New ContributorHello, ArjunTechM.
Thank you for contacting Intel® Memory and Storage support.
This issue is related to FPGA, and we will move your thread to the Intel® FPGA Software support community.
Thank you for your patience and understanding.
Best regards.
Jos B.
Intel® Customer Support Technician
Regular ContributorHi,
You could start here with our GSRD and GHRD:
https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD
For starters, try to boot from QSPI using the prebuilt images:
https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD#Booting_from_QSPI
https://releases.rocketboards.org/2022.07/gsrd/agilex_gsrd/
References:
https://github.com/altera-opensource/ghrd-socfpga
https://github.com/altera-opensource/gsrd-socfpga
Regular ContributorHi,
Any update from your side?
