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Milan_S's avatar
Milan_S
Icon for New Contributor rankNew Contributor
2 months ago

ERROR: Config PwrMgr handoff failed. error -1

Hi,

After switching my Agilex 5 work from Quartus 24.3.1 to Quartus 25.3.0, I encountered the following issue.
When I try to start my SoC platform, instead of the normal boot process (and UART output), I get the following error:

ERROR:   Config PwrMgr handoff failed. error -1
ASSERT:  plat/intel/soc/agilex5/soc/agilex5_power_manager.c:80
BACKTRACE: START: assert
0: EL3: 0xc98
1: EL3: 0xa428
2: EL3: 0x78cc
3: EL3: 0x54f8
4: EL3: 0xb40
5: EL3: 0xe0
BACKTRACE: END: assert

Additional information:
- Booting from QSPI (FPGA-first mode)
- Zephyr OS
- Device: A5ED065BB32AE4SR0
- Board: Atum A5 Evaluation Board
- Normal operating conditions

Hps Boot

3 Replies

  • RolandoS_Altera's avatar
    RolandoS_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    Hello

    The error that you are seeing is observed in the First Stage Boot Loader(FSBL), which corresponds to ATF in this flow. This is related to the SDRAM bring-up. From the hardware configuration,  some settings (stored in the bitrstream in QSPI) are read by the FSBL and this configures some HPS/EMIF registers to bring some peripherals or the SDRAM. In this case, seems that the problem is related to any incorrect configuration in the hardware design in the pss_sram_power_off() function (https://github.com/altera-fpga/arm-trusted-firmware/blob/socfpga_v2.13.0/plat/intel/soc/agilex5/soc/agilex5_power_manager.c#L42), which is reporting a failure.

    Unfortunately, we have not updated the Zephyr GSRD after 24.3, so the instructions in https://altera-fpga.github.io/rel-24.3/embedded-designs/agilex-5/e-series/premium/gsrd_zephyr/ug-zgsrd-agx5e-premium/ have not been tested with Quartus 25.3.

    Now, the failure that you see is observed at ATF stage before Zephyr is launched, and we support some flows that also use ATF as bootloader. The flow described in Direct ATF to Linux Boot (https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-qspi_1)  can be used as a reference to build your hardware desgin and your ATF for 25.3 release. You can build these and then use it with your original Zephyr build instructions and see if your error is not longer seen. You can also compare the HPS configuration in Quartus between your current hardware build and the one that you create using the Direct ATF to Linux Boot and identify any difference that could be creating the error that you are seeing.

    Please let me know if this information helps you to move forward.

    Thanks

    Rolando

    • RolandoS_Altera's avatar
      RolandoS_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      2 months ago

      Hello, I just tried to build a simple Zephyr Hello World application using the  Toolchain setup, GHRD, ATF instructions from https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-qspi_1 together with the Zephyr instructions in the https://altera-fpga.github.io/rel-24.3/embedded-designs/agilex-5/e-series/premium/gsrd_zephyr/ug-zgsrd-agx5e-premium/ and this is working correctly as you can see below:

      NOTICE:  DDR: Reset type is 'Power-On'
      NOTICE:  IOSSM: Calibration success status check...
      NOTICE:  IOSSM: All EMIF instances within the IO96 have calibrated successfully!
      NOTICE:  DDR: Calibration success
      NOTICE:  DDR: ECC is enabled
      NOTICE:  IOSSM: Memory initialized successfully on IO96B
      NOTICE:  ###DDR:init success###
      NOTICE:  DFI interface selected successfully to SDEMMC
      NOTICE:  SOCFPGA: QSPI boot
      NOTICE:  BL2: v2.13.0(release):QPDS25.3_REL_GSRD_PR
      NOTICE:  BL2: Built : 15:51:35, Oct 22 2025
      NOTICE:  BL2: Booting BL31
      NOTICE:  SOCFPGA: Boot Core = 0
      NOTICE:  SOCFPGA: CPU ID = 0
      NOTICE:  SOCFPGA: Setting CLUSTERECTRL_EL1
      NOTICE:  BL31: v2.13.0(release):QPDS25.3_REL_GSRD_PR
      NOTICE:  BL31: Built : 15:51:35, Oct 22 2025
      *** Booting Zephyr OS build b755e7bab5f8 ***
      Secondary CPU core 1 (MPID:0x100) is up
      Secondary CPU core 2 (MPID:0x200) is up
      Secondary CPU core 3 (MPID:0x300) is up
      Hello World! intel_socfpga_agilex5_socdk

      Thanks

      Rolando

       

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 months ago

    KianHinT_altera​ 

    Hi Milan, 

    Could you try the steps listed by Rolando ? I suspect the new Quartus 25.3 have some differences in the HPS handoff data format, thus it will give error(in this case power manager/PwrMgr that requires some config data from FPGA) if there is a mismatch between Quartus generated handoff files and ATF/FSBL version.

    I was thinking probably you will need to regenerate the entire project in Quartus 25.3, then rebuild the ATF, uboot, zephyr that is based on QPDS25.3_REL_GSRD_PR with the 25.3 generated files, similar to what Rolando mentioned in his steps.

    Thanks Rolando for helping out in this case.

    Thanks

    Regards

    Kian