Cyclone V FPGA HPS2FPGA Lightweight bridge timing requirement

I am working on developing the interface between the HPS and our FPGA design through the HPS2FPGA Lightweight bridge, which uses the AXI lite bus protocol. This protocol includes some handshaking control between the master and the slave. I have made some progress and am able to write to a register in the FPGA. However, the write operation cannot be completed. It appears that the HPS is waiting for confirmation. I used Quartus SignalTap (a software logic analyzer) to analyze the timing and found that my design module does send the confirmation to the HPS. Most likely, the problem is caused by some timing requirements for the HPS. I can’t find a document that explains the detailed timing requirements about this interface. I would greatly appreciate your feedback Thanks, Peter.

I hope to understand the timing requirements for following signals:

output wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid

output wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr

output wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen

output wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize

output wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst

output wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock

output wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache

output wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot

output wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid

input wire hps_0_h2f_lw_axi_master_awready, // .awready

output wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid

output wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata

output wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb

output wire hps_0_h2f_lw_axi_master_wlast, // .wlast

output wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid

input wire hps_0_h2f_lw_axi_master_wready, // .wready

input wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid

input wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp

input wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid

output wire hps_0_h2f_lw_axi_master_bready, // .bready

output wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid

output wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr

output wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen

output wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize

output wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst

output wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock

output wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache

output wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot

output wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid

input wire hps_0_h2f_lw_axi_master_arready, // .arready

input wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid

input wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata

input wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp

input wire hps_0_h2f_lw_axi_master_rlast, // .rlast

input wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid

output wire hps_0_h2f_lw_axi_master_rready, // .rready