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BrianSune_Froum's avatar
BrianSune_Froum
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1 year ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
Board Debug
  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 year ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

BrianSune_Froum's avatar
BrianSune_Froum
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1 year ago

@JingyangTeh_Altera @khtan

Final solved the 2K pagesize problem for 2K the precharge time is critical on the settings.

Same Quartus 18.1 just need to tune the parameters more tediously.


And also even w/o the leveling as datasheet mentioned. There are no issues on fly-by design.

Finally saved the batch.

And this info should help other designers until 2030.

  • SueC_Altera's avatar
    SueC_Altera
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    1 year ago

    This is great news, Brian! Thanks for sharing your solution.

    Sue