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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Any Cyclone V soc bare metal startup project settings available?

Hi,

I successfully ran the sample on the rocketboards,

now I want to make my own project,

do you guys have any setting guide for that?

Reguards.

29 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    The .ds file is referring to the debuger script where arm ds used during debugging run time.

    Arm ds will read the script to perform the debugging steps example like setting breakpoint in the script in a function which you specify.

    There are some example that shown in this document using hwlibs example like(Altera-SoCFPGA-HardwareLib-Timer-CV-GNU.tar.gz):

    https://www.rocketboards.org/foswiki/Documentation/SoCEDS


    https://www.rocketboards.org/foswiki/Documentation/SoCEDS

    The MSEL selection is set as referring to page 8 of the document:

    https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/soc-quickstart-v1.0.pdf


    You mentioned that for once you successfully download the spl and initialize the DDR, that is shown on your UART with spl boot up logs?

    Example for my case I program the image binary file(qspi-image.bin) which is a spl+application into the QSPI flash on address 0x000000: quartus_hps -c 1 -o pv -a 0x000000 qspi-image.bin

    My board MSEL will set to boot from QPSI flash. Then application code will load into the DDR and run from DDR address starting 0x00100040

    Anyway just for spl debugging there is this some example of running debugging using arm ds for cyclone V:

    https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Debugging_U_45Boot


    Thanks.

    Regards,

    Aik Eu


    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor

      The error occurs when I do the preload debug.

      doing restore xxx/xx/u-boot-spl.dtb binary &__bss_end.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    I do not have the similar .ds file in my folder directory of my baremetal application from the error you have shown.

    I think the .ds script it trying to run but encounter error based on what is written in the script.

    I would like to test it out with Arm ds. I will find a time to test on the board with arm ds next week.

    At the mean time if used back the timer baremetal example in arm-ds, will it work?


    Thanks.

    Regards,

    Aik Eu


    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor

      I cant even load the spl, it means it cant start at DDR. Once I could but now I cant witht the same steps.

      The ds file is form the cycloneV soc hwlib example from rocketboards.org

      If you succeeded by windows, could you please share the GHRD software folder?

      My environemnt is :
      SOCEDS standard 20.1

      ARM DS 21.1 evaluation

      Quartus 22.1lite

      WSL2 ubuntu 20.04 LTS

    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor

      Hi,

      I solved it, I used the older version U-boot(like the example said 2020.04 would work).

      The newest version 2023.0~2022.10 cant work under my environment though.

      You guys may want to test and fix this maybe?

      Reguards

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    I didnt face the issue of using the latest u-boot. Is it related to compilation issue?

    May I know what is the current state of troubleshooting on ur side?


    Thanks.

    Regards,

    Aik Eu


    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor

      Yes,

      when I use the newest u-boot version and loaded the u-boot-spl the cycloneV soc dev kit board didnt work. I made the u-boot by arm-eabi-gcc linaro 7.5.0 i686 minGW64.

      And I start to use the 2020.04 version and build the u-boot on my another computer(Linux version with Ubuntu 22.04LTS). The spl finally worked.

      I dont know what is the reason but you may have that a try.

      BTW, I downloaded the linaro zip file direct from the github and copy the newlib I installed before for my intelnet here is too bad to finish the whole download.

      I can try to run the whole ./install_linaro.sh when Im free and try again for that case.

      I hope this may help.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    Good to hear that part of the issue has been solved on your side.

    Do let me know regarding the further follow up on your side.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    Do let me know if there is an update on your side.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,



    Do let me know if you already have some follow up regarding your previous working state.



    Thanks.

    Regards,

    Aik Eu


    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor

      Sorry I dont have time right now for other issues of the project.

      And since this issue no longer bothers me you can do what you must to this thread.

      Thank you.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi CAlex,


    Thanks for the respond. I will close this thread for now.


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


    Thanks.

    Regards,

    Aik Eu