Any Cyclone V soc bare metal startup project settings available?

Hi CAlex,

The .ds file is referring to the debuger script where arm ds used during debugging run time.

Arm ds will read the script to perform the debugging steps example like setting breakpoint in the script in a function which you specify.

There are some example that shown in this document using hwlibs example like(Altera-SoCFPGA-HardwareLib-Timer-CV-GNU.tar.gz):

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

The MSEL selection is set as referring to page 8 of the document:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/soc-quickstart-v1.0.pdf

You mentioned that for once you successfully download the spl and initialize the DDR, that is shown on your UART with spl boot up logs?

Example for my case I program the image binary file(qspi-image.bin) which is a spl+application into the QSPI flash on address 0x000000: quartus_hps -c 1 -o pv -a 0x000000 qspi-image.bin

My board MSEL will set to boot from QPSI flash. Then application code will load into the DDR and run from DDR address starting 0x00100040

Anyway just for spl debugging there is this some example of running debugging using arm ds for cyclone V:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Debugging_U_45Boot

Thanks.

Regards,

Aik Eu