Hello, I'm using DE1-SoC with lubuntu 16.04. I'm trying to make a C program to access the HPS resources such as LED, GPIO, etc. """ I was using the kernel from Terasic, and the C program with altera functions (e.g. alt_write_word) to access the HPS resources could be successfully executed. However, from someday, the kernel was corrupted by an unknown reason and the kernel from Terasic was also not working. (The U-boot failed after "Starting Kernel...") So I replaced zImage file from Terasic resource to ghrd provided by releases.rocketboards.org and I could boot the FPGA successfully.(rbf file was not replaced) """ However, the terminal through the serial communication freezes after executing C program with altera functions. That is, the terminal does not show any further logs and does not respond to any commands such as CTRL-C when I run the program with altera functions. I've checked that the program without altera functions (such as, Hello World!) can be successfully executed. Although the terminal freezes, I can still see the RXD LED blinking if I type the keyboard (i.e. sending data to FPGA HPS) Is there any idea to debug this kind of error?

Hello서박사, I’m glad that your problem has been fixed.So I will close this thread if no further questions from you. Best regards, Yoshiaki Saito

ALTERA function fails after execution at C program

12 Replies

Yoshiaki_Altera
Occasional Contributor
4 years ago
Hello 서박사,

Could you please try the following tool to access your LED and GPIO?

https://github.com/pengutronix/memtool

It’s simple physical memory access tool on Linux.

It must executed with sudo or on root user.

Best regards,

Yoshiaki Saito
IntelSupport
Contributor
4 years ago
Hello서박사,

I’m glad that your problem has been fixed.
So I will close this thread if no further questions from you.

Best regards,
Yoshiaki Saito
서박사
Occasional Contributor
4 years ago
Hello Yoshiaki,

Thank you for your prompt response and the suggestion!

I've tried to use memtool from the above link but failed to cross-compile it since my cross-compile environment doesn't have autoconfigure

So I used another source code from the site below to compile memtool:

https://gist.github.com/mike0/2910170

Unfortunately, the read/write operation from/to certain registers (especially, FPGA-related registers) fail.

TChat is, the terminal does not respond to any commands like case the above.

I tried following commands (1 word = 32 bit):

#1

memtool FF001000 1 (read 1 word from 0xFF001000)

Reading 0x1 count starting at address 0xFF001000

0xFF001000: 00000000

#2

memtool FF200000 2 (read 2 words from 0xFF200000, while 0xFF200000 means LEDR)

Reading 0x3 count starting at address 0xFF000000

(freezes)

#3

memtool FF200020=16 (write 32bit word 16 to 0xFF200020, while 0xFF200020 means 7-segment displays register)

Writing 32-bit value 0x16 to address 0xFF200020

(freezes)

#4

memtool FFFEC600 3 (read 3 words from 0xFFFEC600, while 0xFFFEC600 means ARM A9 Private Timer)

Reading 0x3 count starting at address 0xFFFEC600

0xFFFEC600: 00234934 00165135 00000005

#5

memtool FFFEC600 3 (read 3 words again from 0xFFFEC600)

Reading 0x3 count starting at address 0xFFFEC600

0xFFFEC600: 00234934 00138EB5 00000005

The addresses of the registers are based on DE1-SoC_Computer_ARM.pdf

From the above result, should I suppose the FPGA hardware malfunction?

+ More logs using memtool

#6

memtool FFD0501C 3 (read 3 words from 0xFFD0501C, while 0xFFD0501C means FPGA Bridge)
Reading 0x3 count starting at address 0xFFD0501C
[ 68.718423] 8<--- cut here ---

[ 68.725699] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6f0c024
[ 68.733491] pgd = 64d55855
[ 68.736193] [b6f0c024] *pgd=3ffb8831
Bus error (core dumped)

#7

memtool C0000000 1 (read 1 words from 0xC0000000, while 0xC0000000 means SDRAM)

Reading 0x1 count starting at address 0xC0000000

(freezes)
- Yoshiaki_Altera
  Occasional Contributor
  4 years ago
  Hello 서박사,
  
  Thank you for sharing the logs with us.
  
  First of all, you need to confirm Cyclone V SoC register map below.
  
  Cyclone V HPS Register Address Map and Definitions
  
  https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1418687413697.html
  
  In case of #6, FFD0501C and FFD05020 are valid. But FFD05024 is undefined.
  
  If you access undefined area, AXI bus might response SLVERR or DECERR.
  
  The error will cause Bus Error.
  
  In case of the freezes, could you please try these addresses using 'md' command on U-boot?
  
  If you encounter an error, HPS2FPGA and Lightweight HPS2FPGA bridges might be disabled.
  
  Please check brgmodrst register (0xffd0501c).
  
  The bridges should be enabled on U-Boot.
  
  Best regards,
  
  Yoshiaki Saito
  - 서박사
    Occasional Contributor
    4 years ago
    Hello Yoshiaki,
    
    Thank you again for your suggestion.
    
    I've checked the register at the address 0xffd0501c and at the address FF200000 and got the result as follows:
    
    Booting log
    
    U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)
    
    CPU : Altera SOCFPGA Platform
    BOARD : Altera SOCFPGA Cyclone V Board
    I2C: ready
    DRAM: 1 GiB
    MMC: ALTERA DWMMC: 0
    *** Warning - bad CRC, using default environment
    
    In: serial
    Out: serial
    Err: serial
    Skipped ethaddr assignment due to invalid EMAC address in EEPROM
    Net: mii0
    Warning: failed to set MAC address
    
    Hit any key to stop autoboot: 0
    SOCFPGA_CYCLONE5 # md.w FFD05020 2
    ffd05020: 0000 0000 ....
    SOCFPGA_CYCLONE5 # md.w FF200000 1
    ff200000:
    
    (freeze)
    
    As far as I know, if the last 3 bit is low (0), the bridges are enabled.
    
    I've also checked that if FPGA itself is not working properly through operating the FPGA in active-serial mode, but I found that the operation of the FPGA is not the issue.
    
    Please let me know if there is any other method to debug this error.
    
    I appreciate your time and effort. Thank you!
Yoshiaki_Altera
Occasional Contributor
4 years ago
Hello 서박사,

Thank you for the update.

The address of Bridge enable register below is 0xffd0501c, not 0xffd05020.

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067767967.html

Next, you should use correct access size for I/O register, not memory.

For I/O register, the access size is important. If you use wrong size, a result of the access will be unpredicted.

In case of 0xffd0501c, you should use md.l or md command due to 32bit register, not md.w.

Please check the status by typing “md ffd0501c 1”.

Lastly, is it possible that you can share the .qsys file with us just in case?

Best regards,

Yoshiaki Saito
- 서박사
  Occasional Contributor
  4 years ago
  Hello Yoshiaki,
  
  Sorry for the wrong logs for accessing the data register.
  
  I've checked the value at the register which corresponds to the HPS-FPGA bridge changes properly while U-Boot, and the logs are as follows:
  
  commands and logs
  
  U-Boot SPL 2013.01.01 (Oct 12 2016 - 10:38:03)
  BOARD : Altera SOCFPGA Cyclone V Board
  CLOCK: EOSC1 clock 25000 KHz
  CLOCK: EOSC2 clock 25000 KHz
  CLOCK: F2S_SDR_REF clock 0 KHz
  CLOCK: F2S_PER_REF clock 0 KHz
  CLOCK: MPU clock 925 MHz
  CLOCK: DDR clock 400 MHz
  CLOCK: UART clock 100000 KHz
  CLOCK: MMC clock 50000 KHz
  CLOCK: QSPI clock 3613 KHz
  RESET: WARM
  INFO : Watchdog enabled
  SDRAM: Initializing MMR registers
  SDRAM: Calibrating PHY
  SEQ.C: Preparing to start memory calibration
  SEQ.C: CALIBRATION PASSED
  SDRAM: 1024 MiB
  ALTERA DWMMC: 0
  
  U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)
  
  CPU : Altera SOCFPGA Platform
  BOARD : Altera SOCFPGA Cyclone V Board
  I2C: ready
  DRAM: 1 GiB
  MMC: ALTERA DWMMC: 0
  *** Warning - bad CRC, using default environment
  
  In: serial
  Out: serial
  Err: serial
  Skipped ethaddr assignment due to invalid EMAC address in EEPROM
  Net: mii0
  Warning: failed to set MAC address
  
  Hit any key to stop autoboot: 0
  SOCFPGA_CYCLONE5 # fatload mmc 0:1 $fpgadata soc_system.rbf;
  reading soc_system.rbf
  7007204 bytes read in 358 ms (18.7 MiB/s)
  SOCFPGA_CYCLONE5 # fpga load 0 $fpgadata $filesize;
  SOCFPGA_CYCLONE5 # md FFD0501C 1
  ffd0501c: 00000007 ....
  SOCFPGA_CYCLONE5 # run bridge_enable_handoff;
  ## Starting application at 0x3FF795A4 ...
  ## Application terminated, rc = 0x0
  SOCFPGA_CYCLONE5 # md FFD0501C 1
  ffd0501c: 00000000 ....
  SOCFPGA_CYCLONE5 # run mmcload;
  reading zImage
  5676720 bytes read in 286 ms (18.9 MiB/s)
  reading socfpga.dtb
  31245 bytes read in 8 ms (3.7 MiB/s)
  SOCFPGA_CYCLONE5 # run mmcboot;
  ## Flattened Device Tree blob at 00000100
  Booting using the fdt blob at 0x00000100
  reserving fdt memory region: addr=0 size=1000
  Loading Device Tree to 03ff5000, end 03fffa0c ... OK
  
  Starting kernel ...
  
  In addition, .qsys file is compressed to .7z file and attached this reply, so please find it.
  
  It is based on the project "DE1-SoC_Computer " which is provided by Altera University Program.
  
  The .rbf file is based on the attached .qsys file, .dtb file is based on the Terasic Ubuntu image and zImage is provided by releases.rocketboards.org.
  
  I've tried to use all files from Terasic Ubuntu image, but in this case, I couldn't boot the device.
  
  For your information, .dtb file and zImage file are also attached to this reply.
  
  Thank you for your devotion!!
  Computer_System.7z15 KB
  de1soc_ubuntu_1604.7z5 MB
  - Yoshiaki_Altera
    Occasional Contributor
    4 years ago
    Hello Hi서박사,
    
    Basically, you should build DTB from DTS in same Kernel tree.
    
    So could you please try the latest Linux Ubuntu Desktop(2016-12-28) in new SD-CARD again just in case?
    
    Lastly, Bus size of LED is 32 bit as below. You should use md.l or md command to access the port instead of md.w.
    
    2.3.1 Red LED Parallel Port
    
    https://ftp.intel.com/Public/Pub/fpgaup/pub/Intel_Material/18.1/Computer_Systems/DE1-SoC/DE1-SoC_Computer_NiosII.pdf#page=4
    
    Best regards,
    
    Yoshiaki Saito
IntelSupport
Contributor
4 years ago
Hello 서박사,

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Thank you.

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ALTERA function fails after execution at C program

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