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서박사's avatar
서박사
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

ALTERA function fails after execution at C program

Hello, I'm using DE1-SoC with lubuntu 16.04. I'm trying to make a C program to access the HPS resources such as LED, GPIO, etc. """ I was using the kernel from Terasic, and the C program wi...
  • IntelSupport's avatar
    IntelSupport
    4 years ago

    Hello서박사,

    I’m glad that your problem has been fixed.

    So I will close this thread if no further questions from you.

    Best regards,

    Yoshiaki Saito


Yoshiaki_Altera's avatar
Yoshiaki_Altera
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello 서박사,

Thank you for sharing the logs with us.

First of all, you need to confirm Cyclone V SoC register map below.

Cyclone V HPS Register Address Map and Definitions

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1418687413697.html

In case of #6, FFD0501C and FFD05020 are valid. But FFD05024 is undefined.

If you access undefined area, AXI bus might response SLVERR or DECERR.

The error will cause Bus Error.

In case of the freezes, could you please try these addresses using 'md' command on U-boot?

If you encounter an error, HPS2FPGA and Lightweight HPS2FPGA bridges might be disabled.

Please check brgmodrst register (0xffd0501c).

The bridges should be enabled on U-Boot.

Best regards,

Yoshiaki Saito

서박사's avatar
서박사
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello Yoshiaki,

Thank you again for your suggestion.

I've checked the register at the address 0xffd0501c and at the address FF200000 and got the result as follows:

Booting log

U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)

CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1 GiB
MMC: ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address

Hit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 # md.w FFD05020 2
ffd05020: 0000 0000 ....
SOCFPGA_CYCLONE5 # md.w FF200000 1
ff200000:

(freeze)

As far as I know, if the last 3 bit is low (0), the bridges are enabled.

I've also checked that if FPGA itself is not working properly through operating the FPGA in active-serial mode, but I found that the operation of the FPGA is not the issue.

Please let me know if there is any other method to debug this error.

I appreciate your time and effort. Thank you!

  • 서박사's avatar
    서박사
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    For your information,

    In addition, md command failure log is different between the following u-boot command:

    command

    run bridge_enable_handoff;

    log

    ## Starting application at 0x3FF795A4 ...
    ## Application terminated, rc = 0x0

    before the command, md fails as follows:

    command

    md.b FF200000 1

    log

    ff200000:data abort

    MAYBE you should read doc/README.arm-unaligned-accesses

    pc : [<3ff95052>] lr : [<3ff95027>]
    sp : 3ff355b0 ip : 0000001c fp : 00000002
    r10: ff200000 r9 : ff200000 r8 : 3ff35f60
    r7 : 00000000 r6 : 00000001 r5 : 00000001 r4 : 00000001
    r3 : ff200000 r2 : c0000000 r1 : 3ff355bc r0 : 00000009
    Flags: Nzcv IRQs on FIQs off Mode SVC_32
    Resetting CPU ...

    resetting ...

    U-Boot SPL 2013.01.01 (Oct 12 2016 - 10:38:03)
    BOARD : Altera SOCFPGA Cyclone V Board
    CLOCK: EOSC1 clock 25000 KHz
    CLOCK: EOSC2 clock 25000 KHz

    (...reboots automatically)

    after the command, md fails as follows:

    command

    md.b FF200000 1

    log

    ff200000:

    (freezes)

    Thank you!