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K606's avatar
K606
Icon for Contributor rankContributor
1 year ago
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Agilex5 JOP Bitstream Configuration Hang

I am using this guide as a reference to try and add JOP capability to my project. Following this step: 5. Connect the reset and clock to JOP component, also connect it's slave bus to the HPS LW b...
Compilation
  • EstebanV_Altera's avatar
    EstebanV_Altera
    1 year ago

    Hi @K606

    We internally evaluated your issue with the https://www.intel.com/content/www/us/en/support/programmable/articles/000098223.html and concluded they are not related (this is more related with the use of the JTAG chain, that does not prevents the HPS from booting). Your u-boot should be going through...

    So, please, program your board using the .sof and this would give you and indication of why the "rbf" load is hanging.

    Sorry for the delay in checking this out.

    ~E.V.

EstebanV_Altera's avatar
EstebanV_Altera
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi @K606 ,

This is my recommendation:

1. Once your SOF is generated after (Quartus Compilation).Re-generate the pair JIC/RBF. Using the u-boot-spl-dtb.hex file generated from the YOCTO build.

2. Flash your board with the new <name>.hps.jic, and compile the Yocto build so the fresh <name>.core.rbf is added to the kernel.itb file in the SD card boot partition.

Often this failure happens because there is a mistmatch with the generated jic/rbf pair, so you have to be consistent and use the ones generated from:

quartus_pfg \ -c <name>.sof ghrd_a5ed065bb32ae6sr0.jic \

-o device=MT25QU128 \

-o flash_loader=A5ED065BB32AE6SR0 \

-o hps_path=u-boot-spl-dtb.hex \

-o mode=ASX4 \

-o hps=1

Please, give it a try and let me know.

~E.V.

  • K606's avatar
    K606
    Icon for Contributor rankContributor
    1 year ago

    Hi @EstebanV_Altera,

    Thanks for your fast reply!

    Apologies, forgot to mention that I am booting via TFTP, so do not need the SD card for anything except the section of the UBOOT script which fetches and boots the FPGA bitstream.

    I have re-generated the .rbf in this way you suggest multiple times already, but each time I have this same hang!

    Do you think it's possible to test the design on your end via TFTP? In the meantime - I will flash the new JIC.

    Many thanks,

    K