Forum Discussion
K606
Contributor
1 year agoAgilex5 JOP Bitstream Configuration Hang
I am using this guide as a reference to try and add JOP capability to my project. Following this step: 5. Connect the reset and clock to JOP component, also connect it's slave bus to the HPS LW b...
- 1 year ago
Hi @K606
We internally evaluated your issue with the https://www.intel.com/content/www/us/en/support/programmable/articles/000098223.html and concluded they are not related (this is more related with the use of the JTAG chain, that does not prevents the HPS from booting). Your u-boot should be going through...
So, please, program your board using the .sof and this would give you and indication of why the "rbf" load is hanging.
Sorry for the delay in checking this out.
~E.V.
EstebanV_Altera
Occasional Contributor
1 year ago@K606 can you share what you are seeing in after "fpga load... " command?
Could you please clarify if you are using Quartus 24.2?
K606
Contributor
1 year agoHi Esteban,
Yes this is my log in u-boot:
In fact, I am using Quartus 24.3.
Many thanks,
K