Agilex 5 Multiboot SPL Fails to Probe QSPI

A bit more information, i am not sure why UBOOT Proper and linux works for you. If the Frequency is wrong, it would have failed from the start.

Can you dump your device tree for Linux here?

The design is as follow so that you can debug this on your own.

1. The SDM gets the AS_CLK from your QHIP platform designer setting
2. The SDM calculates the QSPI REF clock , here 500MHz based on your 125MHz
3. The FSBL UBOOT gets the QSPI REF Clock via mailbox as you saw.
4. The FSBL writes the QSPI REF clock to scratch boot register which is later shared to the UBOOT Proper
5. The UBOOT proper should still use 500MHz as the ref clock.
6. The Kernel gets the 500MHz by running a script in UBOOT Proper CLI, which updates the Linux kernel's freq.

SOCFPGA_AGILEX # fdt addr 0x8000000

Working FDT set to 8000000

SOCFPGA_AGILEX # run linux_qspi_enable              

SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB

Enabling QSPI at Linux DTB...

Working fdt: 08000000

QSPI clock frequency updated

SOCFPGA_AGILEX #

Can you place printf to determine why the spi flash probe fails? Can you print out the ref_clk_hz? I would like to see whether the UBOOT Proper uses a different ref clock than the UBOOT SPL.  And, also to double confirm the ref freq used. 

hi,

You need to set the AS_CLK to a frequency less than 80MHz which is your NOR flash's max frequency. 

The 500MHz is the QSPI REF clock which is 4 times the AS_CLK. This is an internal design where the SDM chooses the REF clock based on your AS_CLK input. Try to pick another AS_CLK less than 80MHz in the Quartus GUI below.

Dear all,

To clarify:
- I am using a custom board.
- I am able to access QSPI from U-Boot proper using the dts from the previous post.
- I am able to access QSPI from Linux.
- I am not able to access QSPI from U-Boot SPL.
- The QSPI Flash only contains U-Boot SPL and SDM Firmware.
- The U-Boot Proper, FPGA image, and Linux kernel image are stored on the SD Card. U-Boot Proper is stored on FAT partition and is loaded by U-Boot SPL.
- The QSPI Flash from the DTS (MT25QU256) is correct and you are correct in saying that it is only 32MB. We have 3 partitions (factory + 2 others) of 8MB each. During updates the .rpd file is around 800kB so (assuming .rpd doesn't contain compressed images?) the size should be sufficient.

Yes, the message "QSPI: Reference clock at 500000 kHz" could be the culprit. The flash only supports up to 80 MHz. I tried lowering this setting but I couldn't figure out which setting to change. Can you help here?
From the u-boot source code I see that the SPL gets this frequency via mailbox request to SDM (arch/arm/mach-socfpga/mailbox_s10.c:mbox_qspi_open()). So it could be a setting in Quartus/Qsys or in the u-boot dts.
I've checked both but I don't find anything that sets the clock to 500MHz.
- In my dts I set the speed to 6,25 MHz (see previous post).
- In the decompiled u-boot dtb I see soc/clocks/qspi-clk { clock-frequency = <0xbebc200>; } (200MHz)
- In Qsys I see "Peripheral PLL C3" and "PSI Ref" at 500MHz. As there are a number of other clocks derived from those I can't easily test changing this value.
- In Quartus the "Active serial clock source" is set to 125MHz.

Kind Regards,
Eric Opitz

Hi EricOpitz 

Do you have any update for the question in the previous comment?

hi,

I think your Device tree could be the culprit. It does not seem right. Let us go through the questions below.

Can i seek clarification on your statement "So far I've been able to access QSPI from U-Boot and Linux."? Are you able to access QSPSI in UBOOT-proper (SSBL) and Linux ? The QSPI only failed during SPL RSU? I am a bit confuse here.  Let me assume you did not actually see QSPI working on your target board.

What board are you using? My assumption is a custom board.

The NOR Flash you are using is only 32MB.  "  compatible = "micron,mt25qu256a", "jedec,spi-nor";" Your flash is a bit too small to support both RSU and QSPI boot for HPS.  Is this the correct Flash device? Is your Device tree correct?

Typically, the RSU takes up to 64MB (we could go lower if there is no need to support multiple RSU slots), and the remaining partitions cater to the HPS secondary boot images like SSBL UBOOT, Linux kernel and the Linux ROOTFS in UBIFS format. The SSBL UBOOT is of course a fixed address in the NOR flash so, the SPL could locate it during boot-up. The SSBL UBOOT address is CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 (from  UBOOT source, configs/socfpga_agilex5_defconfig)  

The partitions that we used for the Altera premium devkit is shown below. Of course this is just an example. You are free to change the partition but you may have to modify the Device tree and UBOOT config especially the U_BOOT offset address.

Are you booting everything from QSPI NOR flash?  

Also the spi-max-frequency is different.

Also, the Flash partition seems different too.

Also, "QSPI: Reference clock at 500000 kHz" <- The QSPI clock is 500MHz which is different than the one in your DT.

Is this correct? Is this your custom board?

The official GSRD NOR flash is 

https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2025.10/arch/arm/dts/socfpga_agilex5_socdk.dts 

flash0: flash@0 {

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "mt25qu02g";

                reg = <0>;

                spi-max-frequency = <100000000>;

                m25p,fast-read;

                cdns,page-size = <256>;

                cdns,block-size = <16>;

                cdns,read-delay = <1>;

                cdns,tshsl-ns = <50>;

                cdns,tsd2d-ns = <50>;

                cdns,tchsh-ns = <4>;

                cdns,tslch-ns = <4>;