Forum Discussion
Occasional ContributorAgilex 5 Multiboot SPL Fails to Probe QSPI
Dear all,
I was able to find a solution to this issue. Apparently my defconfig was the culprit as it was based on an older QPDS version. Adding the defconfig entries from the QPDS25.1 solved the problem. The Active Serial Clock speed was not the issue and I left it at the QPDS25.1 default (125 MHz).
Here are the changes to my defconfig. I don't know which change solved the issue:
Removed:
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x04100000
CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y
CONFIG_CMD_SF=y
CONFIG_DOS_PARTITION=y
CONFIG_SPL_DOS_PARTITION=y
CONFIG_CMD_NAND=n
CONFIG_CMD_NAND_TRIMFFS=n
CONFIG_CMD_NAND_LOCK_UNLOCK=n
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_UBIFS=n
CONFIG_MTD_UBI=n
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_ENV_IS_IN_UBI=n
CONFIG_FPGA_INTEL_PR=y
CONFIG_MTD=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=n
CONFIG_UBI_SILENCE_MSG=n
CONFIG_DM_ETH=y
CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_SPL_STACK=0x73000
CONFIG_MTD_RAW_NAND=n
CONFIG_SPL_NAND_SUPPORT=n
CONFIG_SPL_NAND_FRAMEWORK=n
CONFIG_NAND_BOOT=n
CONFIG_NAND_DENALI_DT=n
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT_HUSH_PS2="> "
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_LZO=y
CONFIG_CMD_DHCP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_ISSI=yAdded:
CONFIG_NR_DRAM_BANKS=3
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_ENV_IS_IN_UBI=n
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="kernel.itb"
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_MTD=y
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
CONFIG_SPL_STACK=0x71000
CONFIG_MTD_RAW_NAND=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_FRAMEWORK=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0x72000
CONFIG_HANDOFF=yI took your advice and added some log messages to u-boot:
- I tested this on the arrow dev kit
- I used version QPDS25.1
- I activated multiboot and set QSPI Ownership to HPS
- I added some debug messagesFrom the log you can see that the speed is retrieved from the SDM and this value is used in cadence_spi_probe(). But afterwards there are two more calls to cadence_spi_set_speed() with 100 MHz (probably from dts) and 1 MHz (probably from CONFIG_SF_DEFAULT_SPEED) respectively. Therefore I think the actual speed is 1 MHz. Perhaps you can verify this and adapt the log message "QSPI: Reference clock at 500000 kHz".
is_ddr_csr_clkgen_locked: ddr csr io96b_0 clkgenA is successfully locked
io96b_cal_status: Calibration for IO96B instance 0x18400400 done at 0 msec!
init_mem_cal: Initial DDR calibration IO96B_0 succeed
DDR: Calibration success
io96b_mb_init: num_instance 1
io96b_mb_init: get memory interface IO96B 0
io96b_mb_init: IO96B 0 mem_interface 0: ip_type_ret: 0x1
io96b_mb_init: IO96B 0 mem_interface 0: instance_id_ret: 0x0
io96b_mb_init: IO96B 0: num_mem_interface: 0x1
LPDDR4: 1024 MiB
ecc_enable_status: ECC enable status: 0
DDR: size check success
DDR: firewall init success
DDR: init success
QSPI: Reference clock at 500000 kHz
Bloblist at 72000 not found (err=-2)
WDT: Not starting watchdog@10d00200
Trying to boot from MMC1
get_spl_slot
spi_flash_probe
CONFIG_SF_DEFAULT_BUS. 0
CONFIG_SF_DEFAULT_CS. 0
CONFIG_SF_DEFAULT_SPEED. 1000000
CONFIG_SF_DEFAULT_MODE. 8195
cadence_spi_probe
priv->ref_clk_hz = 500000000
cadence_spi_probe - return
cadence_spi_set_speed
hz = 100000000
cadence_spi_set_speed - return
cadence_spi_set_speed
hz = 1000000
cadence_spi_set_speed - return
RSU current image: 0x01000000
RSU state: 0x00000000
RSU error location: 0x00000000
RSU error details: 0x00000000
RSU: Partition 'BOOT_INFO' start=0x00000000 length=0x00210000
RSU: Partition 'FACTORY_IMAGE' start=0x00210000 length=0x00800000
RSU: Partition 'image1' start=0x01000000 length=0x00800000
RSU: Partition 'image2' start=0x01800000 length=0x00800000
RSU: Partition 'SPT0' start=0x00a10000 length=0x00008000
RSU: Partition 'SPT1' start=0x00a18000 length=0x00008000
RSU: Partition 'CPB0' start=0x00a20000 length=0x00008000
RSU: Partition 'CPB1' start=0x00a28000 length=0x00008000
get_spl_slot - return
rsu_spl_mmc_filename, filename: u-boot_image1.itb
spl_mmc_load_image: Boot from filename: u-boot_image1.itb
spl_load_image_fat: error reading image u-boot_image1.itb, err - -5
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###Kind Regards,
Eric Opitz
Occasional ContributorDear all,
To clarify:
- I am using a custom board.
- I am able to access QSPI from U-Boot proper using the dts from the previous post.
- I am able to access QSPI from Linux.
- I am not able to access QSPI from U-Boot SPL.
- The QSPI Flash only contains U-Boot SPL and SDM Firmware.
- The U-Boot Proper, FPGA image, and Linux kernel image are stored on the SD Card. U-Boot Proper is stored on FAT partition and is loaded by U-Boot SPL.
- The QSPI Flash from the DTS (MT25QU256) is correct and you are correct in saying that it is only 32MB. We have 3 partitions (factory + 2 others) of 8MB each. During updates the .rpd file is around 800kB so (assuming .rpd doesn't contain compressed images?) the size should be sufficient.
Yes, the message "QSPI: Reference clock at 500000 kHz" could be the culprit. The flash only supports up to 80 MHz. I tried lowering this setting but I couldn't figure out which setting to change. Can you help here?
From the u-boot source code I see that the SPL gets this frequency via mailbox request to SDM (arch/arm/mach-socfpga/mailbox_s10.c:mbox_qspi_open()). So it could be a setting in Quartus/Qsys or in the u-boot dts.
I've checked both but I don't find anything that sets the clock to 500MHz.
- In my dts I set the speed to 6,25 MHz (see previous post).
- In the decompiled u-boot dtb I see soc/clocks/qspi-clk { clock-frequency = <0xbebc200>; } (200MHz)
- In Qsys I see "Peripheral PLL C3" and "PSI Ref" at 500MHz. As there are a number of other clocks derived from those I can't easily test changing this value.
- In Quartus the "Active serial clock source" is set to 125MHz.
Kind Regards,
Eric Opitz
Regular Contributor- EricOpitz
Dear all,
I was able to find a solution to this issue. Apparently my defconfig was the culprit as it was based on an older QPDS version. Adding the defconfig entries from the QPDS25.1 solved the problem. The Active Serial Clock speed was not the issue and I left it at the QPDS25.1 default (125 MHz).
Here are the changes to my defconfig. I don't know which change solved the issue:
Removed:
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x04100000
CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y
CONFIG_CMD_SF=y
CONFIG_DOS_PARTITION=y
CONFIG_SPL_DOS_PARTITION=y
CONFIG_CMD_NAND=n
CONFIG_CMD_NAND_TRIMFFS=n
CONFIG_CMD_NAND_LOCK_UNLOCK=n
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_UBIFS=n
CONFIG_MTD_UBI=n
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_ENV_IS_IN_UBI=n
CONFIG_FPGA_INTEL_PR=y
CONFIG_MTD=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=n
CONFIG_UBI_SILENCE_MSG=n
CONFIG_DM_ETH=y
CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_SPL_STACK=0x73000
CONFIG_MTD_RAW_NAND=n
CONFIG_SPL_NAND_SUPPORT=n
CONFIG_SPL_NAND_FRAMEWORK=n
CONFIG_NAND_BOOT=n
CONFIG_NAND_DENALI_DT=n
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT_HUSH_PS2="> "
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_LZO=y
CONFIG_CMD_DHCP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_ISSI=yAdded:
CONFIG_NR_DRAM_BANKS=3
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_ENV_IS_IN_UBI=n
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="kernel.itb"
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_MTD=y
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
CONFIG_SPL_STACK=0x71000
CONFIG_MTD_RAW_NAND=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_FRAMEWORK=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0x72000
CONFIG_HANDOFF=yI took your advice and added some log messages to u-boot:
- I tested this on the arrow dev kit
- I used version QPDS25.1
- I activated multiboot and set QSPI Ownership to HPS
- I added some debug messagesFrom the log you can see that the speed is retrieved from the SDM and this value is used in cadence_spi_probe(). But afterwards there are two more calls to cadence_spi_set_speed() with 100 MHz (probably from dts) and 1 MHz (probably from CONFIG_SF_DEFAULT_SPEED) respectively. Therefore I think the actual speed is 1 MHz. Perhaps you can verify this and adapt the log message "QSPI: Reference clock at 500000 kHz".
is_ddr_csr_clkgen_locked: ddr csr io96b_0 clkgenA is successfully locked
io96b_cal_status: Calibration for IO96B instance 0x18400400 done at 0 msec!
init_mem_cal: Initial DDR calibration IO96B_0 succeed
DDR: Calibration success
io96b_mb_init: num_instance 1
io96b_mb_init: get memory interface IO96B 0
io96b_mb_init: IO96B 0 mem_interface 0: ip_type_ret: 0x1
io96b_mb_init: IO96B 0 mem_interface 0: instance_id_ret: 0x0
io96b_mb_init: IO96B 0: num_mem_interface: 0x1
LPDDR4: 1024 MiB
ecc_enable_status: ECC enable status: 0
DDR: size check success
DDR: firewall init success
DDR: init success
QSPI: Reference clock at 500000 kHz
Bloblist at 72000 not found (err=-2)
WDT: Not starting watchdog@10d00200
Trying to boot from MMC1
get_spl_slot
spi_flash_probe
CONFIG_SF_DEFAULT_BUS. 0
CONFIG_SF_DEFAULT_CS. 0
CONFIG_SF_DEFAULT_SPEED. 1000000
CONFIG_SF_DEFAULT_MODE. 8195
cadence_spi_probe
priv->ref_clk_hz = 500000000
cadence_spi_probe - return
cadence_spi_set_speed
hz = 100000000
cadence_spi_set_speed - return
cadence_spi_set_speed
hz = 1000000
cadence_spi_set_speed - return
RSU current image: 0x01000000
RSU state: 0x00000000
RSU error location: 0x00000000
RSU error details: 0x00000000
RSU: Partition 'BOOT_INFO' start=0x00000000 length=0x00210000
RSU: Partition 'FACTORY_IMAGE' start=0x00210000 length=0x00800000
RSU: Partition 'image1' start=0x01000000 length=0x00800000
RSU: Partition 'image2' start=0x01800000 length=0x00800000
RSU: Partition 'SPT0' start=0x00a10000 length=0x00008000
RSU: Partition 'SPT1' start=0x00a18000 length=0x00008000
RSU: Partition 'CPB0' start=0x00a20000 length=0x00008000
RSU: Partition 'CPB1' start=0x00a28000 length=0x00008000
get_spl_slot - return
rsu_spl_mmc_filename, filename: u-boot_image1.itb
spl_mmc_load_image: Boot from filename: u-boot_image1.itb
spl_load_image_fat: error reading image u-boot_image1.itb, err - -5
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###Kind Regards,
Eric Opitz
SueC_AlteraContributor
Thanks for posting the solution. Is there anyway you can think of this error could be avoided or how we could prevent people from seeing this problem?
Thanks,
Sue
