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K606
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1 year ago
Solved

Agilex 5 EMAC to EMAC : Driver error

I am trying to ping one EMAC from another, and have instantiated the following in the HPS: These are exported to the top level, then connected as followed: // https://www.intel.com/content/...
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  • K606's avatar
    K606
    1 year ago

    Solved: bring MAC signals up a module

K606's avatar
K606
Icon for Contributor rankContributor
1 year ago

Hi thanks for the resources!

yes no problem, here is the .dtsi:

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2023, Intel Corporation
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-agilex5.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/agilex5-clock.h>

/ {
	compatible = "intel,socfpga-agilex";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x80000000 0x0 0x2000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x100>;
			next-level-cache = <&L2>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x200>;
			next-level-cache = <&L2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x300>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			next-level-cache = <&L3>;
		};

		L3: l3-cache {
			compatible = "cache";
		};

	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	intc: interrupt-controller@1d000000 {
		compatible = "arm,gic-v3", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells =<2>;
		interrupt-controller;
		#redistributor-regions = <1>;
		label = "GIC";
		status = "okay";
		ranges;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x0 0x1d000000 0 0x10000>,
			<0x0 0x1d060000 0 0x100000>;

		its: msi-controller@1d040000 {
			compatible = "arm,gic-v3-its";
			reg = <0x0 0x1d040000 0x0 0x20000>;
			label = "ITS";
			msi-controller;
			status = "okay";
		};
	};

	/* Clock tree 5 main sources*/
	clocks {
		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		cb_intosc_ls_clk: cb-intosc-ls-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		f2s_free_clk: f2s-free-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		osc1: osc1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		qspi_clk: qspi-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	usbphy0: usbphy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		base_fpga_region {
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr: clock-controller@10d10000 {
			compatible = "intel,agilex5-clkmgr";
			reg = <0x10d10000 0x1000>;
			#clock-cells = <1>;
		};

		gmac0: ethernet@10810000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10810000 0x3500>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac0_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			altr,smtg-hub;
			iommus = <&smmu 1>;

			status = "disabled";

			stmmac_axi_emac0_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac0_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac0_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		gmac1: ethernet@10820000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10820000 0x3500>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac1_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
			altr,smtg-hub;
			iommus = <&smmu 2>;

			status = "disabled";

			stmmac_axi_emac1_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac1_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac1_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		gmac2: ethernet@10830000 {
			compatible = "altr,socfpga-stmmac-a10-s10",
				     "snps,dwxgmac-2.10",
				     "snps,dwxgmac";
			reg = <0x10830000 0x3500>;
			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq",
					  "macirq_tx0",
					  "macirq_tx1",
					  "macirq_tx2",
					  "macirq_tx3",
					  "macirq_tx4",
					  "macirq_tx5",
					  "macirq_tx6",
					  "macirq_tx7",
					  "macirq_rx0",
					  "macirq_rx1",
					  "macirq_rx2",
					  "macirq_rx3",
					  "macirq_rx4",
					  "macirq_rx5",
					  "macirq_rx6",
					  "macirq_rx7";
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			mac-address = [00 00 00 00 00 00];
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <64>;
			snps,perfect-filter-entries = <64>;
			snps,axi-config = <&stmmac_axi_emac2_setup>;
			snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
			snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
			snps,pbl = <32>;
			snps,pblx8;
			snps,multi-irq-en;
			snps,tso;
			snps,rx-vlan-offload;
			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
			altr,smtg-hub;
			iommus = <&smmu 3>;

			status = "disabled";

			stmmac_axi_emac2_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <31>;
				snps,rd_osr_lmt = <31>;
				snps,blen = <0 0 0 32 16 8 4>;
			};

			mtl_rx_emac2_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				snps,rx-sched-sp;
				queue0 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x0>;
				};
				queue1 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x1>;
				};
				queue2 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x2>;
				};
				queue3 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x3>;
				};
				queue4 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x4>;
				};
				queue5 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x5>;
				};
				queue6 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x6>;
				};
				queue7 {
					snps,dcb-algorithm;
					snps,map-to-dma-channel = <0x7>;
				};
			};

			mtl_tx_emac2_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				snps,tx-queues-with-coe = <2>;
				snps,tx-sched-wrr;
				queue0 {
					snps,weight = <0x09>;
					snps,dcb-algorithm;
				};
				queue1 {
					snps,weight = <0x0A>;
					snps,dcb-algorithm;
				};
				queue2 {
					snps,weight = <0x0B>;
					snps,dcb-algorithm;
				};
				queue3 {
					snps,weight = <0x0C>;
					snps,dcb-algorithm;
				};
				queue4 {
					snps,weight = <0x0D>;
					snps,dcb-algorithm;
				};
				queue5 {
					snps,weight = <0x0E>;
					snps,dcb-algorithm;
				};
				queue6 {
					snps,weight = <0x0F>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
				queue7 {
					snps,weight = <0x10>;
					snps,dcb-algorithm;
					snps,tbs-enable;
				};
			};
		};

		i2c0: i2c@10c02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02800 0x100>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@10c02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02900 0x100>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@10c02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02a00 0x100>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@10c02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02b00 0x100>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@10c02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02c00 0x100>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i3c0: i3c@10da0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da0000 0x1000>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I3C0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			status = "disabled";
		};

		i3c1: i3c@10da1000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da1000 0x1000>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst I3C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			status = "disabled";
		};

		gpio0: gpio@10c03200 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x10c03200 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@10C03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x10C03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		mmc: mmc0@10808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "intel,agilex5-sd4hc", "cdns,sd4hc";
			reg = <0x10808000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <0x800>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMCLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			status = "disabled";
		};

		nand: nand-controller@10b80000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cdns,hp-nfc";
			reg = <0x10b80000 0x10000>,
					<0x10840000 0x1000>;
			reg-names = "reg", "sdma";
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
			clock-names = "nf_clk";
			cdns,board-delay-ps = <4830>;
			iommus = <&smmu 4>;
			status = "disabled";
		};

		ocram: sram@00000000 {
			compatible = "mmio-sram";
			reg = <0x00000000 0x80000>;
		};

		dmac0: dma-controller@10DB0000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0x10DB0000 0x500>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
				 <&clkmgr AGILEX5_L4_MP_CLK>;
			clock-names = "core-clk", "cfgr-clk";
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <32767 32767 32767 32767>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <8>;
			snps,dma-40-bit-mask;
			iommus = <&smmu 8>;
			status = "okay";
		};

		dmac1: dma-controller@10DC0000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0x10DC0000 0x500>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
				 <&clkmgr AGILEX5_L4_MP_CLK>;
			clock-names = "core-clk", "cfgr-clk";
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <32767 32767 32767 32767>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <8>;
			snps,dma-40-bit-mask;
			iommus = <&smmu 9>;
			status = "okay";
		};

		rst: rstmgr@10d11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0x10d11000 0x100>;
		};

		smmu: iommu@16000000 {
			compatible = "arm,smmu-v3";
			reg = <0x16000000 0x30000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror", "priq";
			dma-coherent;
			#iommu-cells = <1>;
			status = "disabled";
		};

		spi0: spi@10da4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da4000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			dmas = <&dmac0 16>, <&dmac0 17>;
			dma-names ="tx", "rx";
			status = "disabled";
		};

		spi1: spi@10da5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da5000 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			dmas = <&dmac0 20>, <&dmac0 21>;
			dma-names ="tx", "rx";
			status = "disabled";
		};

		sysmgr: sysmgr@10d12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0x10d12000 0x500>;
		};

		timer0: timer0@10c03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10c03000 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@10c03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10c03100 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@10d00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10d00000 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@10d00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10d00100 0x100>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial@10c02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02000 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
		};

		uart1: serial@10c02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02100 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
		};

		usb0: usb@10b00000 {
			compatible = "snps,dwc2";
			reg = <0x10b00000 0x40000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
			clock-names = "otg";
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb31: usb1@11000000 {
			compatible = "intel,agilex5-dwc3";
			reg = <0x11000000 0x100000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
				 <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc3", "dwc3-ecc";
			status = "disabled";

			dwc3_0: usb@11000000{
				compatible = "snps,dwc3";
				reg = <0x11000000 0x100000>;
				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&smmu 7>;
				phys = <&usbphy0>, <&usbphy0>;
				phy-names = "usb2-phy", "usb3-phy";
				maximum-speed = "super-speed-plus";
				snps,dis_u2_sysphy-quirk;
				snps,dma_set_40_bit_mask_quirk;
			};
		};

		eccmgr {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global_sbe", "io96b0" , "io96b1",
					  "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu";
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			ocram-ecc@108cc000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0x108cc000 0x100>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb0-ecc@108c4000 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn0-rx-ecc@108c0000 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn0-tx-ecc@108c0400 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn1-rx-ecc@108c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0800 0x100>;
				altr,ecc-parent = <&gmac1>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn1-tx-ecc@108c0C00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c0C00 0x100>;
				altr,ecc-parent = <&gmac1>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn2-rx-ecc@108c1000 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c1000 0x100>;
				altr,ecc-parent = <&gmac2>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			};

			tsn2-tx-ecc@108c1400 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0x108c1400 0x100>;
				altr,ecc-parent = <&gmac2>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram0-ecc@108c4C00 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4C00 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram1-ecc@108c4800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4800 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb31-ram2-ecc@108c4400 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0x108c4400 0x100>;
				altr,ecc-parent = <&usb31>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
			};

			io96b0-ecc {
				compatible = "altr,socfpga-io96b-ecc";
				reg = <0x18400000 0x1000>;
				interrupts = <95 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			io96b1-ecc {
				compatible = "altr,socfpga-io96b-ecc";
				reg = <0x18800000 0x1000>;
				interrupts = <120 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			sdm-qspi-ecc@10a22000 {
				compatible = "altr,socfpga-sdm-qspi-ecc";
				reg = <0x10a22000 0x100>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			};

			cram-seu@0 {
				compatible = "altr,socfpga-cram-seu";
				reg = <0x0 0x0>;
			};
		};

		watchdog0: watchdog@10d00200 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00200 0x100>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@10d00300 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00300 0x100>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@10d00400 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00400 0x100>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@10d00500 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00500 0x100>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};
		watchdog4: watchdog@10d00600 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00600 0x100>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst WATCHDOG4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		qspi: spi@108d2000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x108d2000 0x100>,
			      <0x10900000 0x100000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;
			status = "disabled";
		};

		firmware {
			svc {
				compatible = "intel,agilex5-svc";
				method = "smc";
				memory-region = <&service_reserved>;
				iommus = <&smmu 10>;
				altr,smmu_enable_quirk;

				fpga_mgr: fpga-mgr {
					compatible = "intel,agilex5-soc-fpga-mgr";
				};

				fcs: fcs {
					compatible = "intel,agilex-soc-fcs";
					platform = "agilex";
				};

				temp_volt: hwmon {
					compatible = "intel,soc64-hwmon";
				};
			};
		};
	};
};

Many thanks,

K