Forum Discussion

binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Xcelium support for Agilex P-tile PCIe simulations

Hi there, I am creating a PCIe controller targeting Agilex F series device. Wanted to run the example design on Cadence Xcelium simulator. When I ran the generated script for Xcelium, I got the belo...
Simulation
  • binupr's avatar
    binupr
    3 years ago

    Hi Wincent,

    Apologies for the delay in responding to your prior follow-up email.

    Yes, you can close this ticket.

    Thank you for the support.

    Regards

    Binu

binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Wincent,

Thanks for confirming the R-Tile Xcelium support. I should have clarified regarding simulation time.

My question was regarding simulation time of the provided PIO example design. To give you context, I crated the R-Tile IP for AGIB027R29A1E2VR3 in below PCIe mode:

  • 1x16, 1024, TLP Bypass downstream

When I ran simulation, I can see it no longer reports the previous error and proceeds to simulation, but the simulation got hung at a particular point(screenshot below for reference). I cleaned project and re-ran couple of times and had the same issue. The simulation has been hanging now for more than 10 hours.

Could you check with your development team regarding this? Basically, I want to have a confirmation that this hanging issue is not due to any Xcelium compatibility with the OPN.

Thanks

Binu