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Altera_Forum's avatar
Altera_Forum
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15 years ago

WYSIWYG I/O Primitives Error

Hello all:

I am building a simple design on the Stratix II GX Audio Video Development Board, and am running into an error. I have the one-wire interface component giving me access to the dip switches, leds, etc., and I am trying to implement an instance of the altddio_out megafunction. I would like to use the dip switches to provide one-bit data to the output signal on either edge of the clock. I then want to update an LED with this data.

I have the system in place and working, (well, compiling), all but the LED output. For some reason, whenever I try to use the output of the ddio component to also route back to the input of the one-wire interface (OWI) component (to update the LED) I get an error that says:

Error: padio port of the output WYSIWYG I/O primitive "ddio_one:ddio_one_i|altddio_out:altddio_out_component|ddio_out_nad:auto_generated|dataout[0]" is not directly connected to a top-level output pin

The value is sent to a top-level output pin, and when I take out the line that also routes to the OWI, it compiles fine.

When I try to enable the SignalTap analyzer to see if my altddio function is working properly, the same error occurs.

I am just wondering if there is something special about the megafunction that I am missing, or if anyone has run into this before. Thank you very much for any assistance.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I'm motivated to believe the Quartus error message about missing top-level connection of the altddio instance. To understand, how this could happen, I would like to see the respective design part. Sometimes error messages related to connectivity are caused by a different issue, e.g. when the respective function is removed in compilation, because it misses an effective driving signal.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Ok. Should I private message my verilog to you? Or is there something I could post here?