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SSebi's avatar
SSebi
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5 years ago

Wrong synthesis result appending Bits, Quartus 20.1

I have this following implementation of a shift left operation. I know that this implementation is weird or may not be synthesizable because the size of the cResult constant depends on the shift widt...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Sebi,


What is the type of QP you were using to compile? Lite,Std or Pro?


Thanks,

Regards


  • SSebi's avatar
    SSebi
    Icon for New Contributor rankNew Contributor
    5 years ago

    It was tested with the Lite version and a Max 10 FPGA:

    Quartus Prime Version: 20.1.0 Build 711 06/05/2020 SJ Lite Edition
Device: 10M50SAE144C8G