Wrong mapping of overloaded functions in Quartus 24.1 Pro

Hi,

I'm stuck with a weird error in the new Quartus 24.1.0 Build 115 SC Pro Edition.

I defined two functions with the same name but a different signature:

pure function from_my_bool_a(data : in my_bool_at) return std_logic_vector is
    variable res_v : std_logic_vector(data'length*1-1 downto 0);
  begin
    res_v := (others => '0');
    for idx4_v in data'range loop
      res_v(idx4_v) := data(idx4_v);
    end loop;
    return res_v;
  end function;
  
  pure function from_my_bool_a(data : in my_bool_at; size : in integer) return std_logic_vector is -- line 27: warning occurs here
    variable data_v : std_logic_vector(size-1 downto 0);
  begin
    data_v := (others => '0'); -- line 30: error occurs here
    data_v(0 downto 0) := from_my_bool_a(data);
    return data_v;
  end function;

I use one of them to connect a std_logic_vector signal to the output of a module like this:

U_MODULE: entity work.module
    generic map (
		port_width => port_width
	 )
	port map (
		in_a(0) => a,
		from_my_bool_a(out_b) => b
	);

When compiling, this leads to the following warning and error:

Warning(16759): VHDL warning at top_level.vhd(27): formal port or parameter "size" has no actual or default value 
Error(13736): VHDL aggregate error at top_level.vhd(30): OTHERS choice used in aggregate for unconstrained record or array type is not supported 

It seems that Quartus tries to use the function with the additional size parameter here. Which is wrong in my oppinion.
Strangely, the project compiles fine when I change the order in which I define the two functions.

What's wrong here? Is this a compiler bug?

I added a minimal working example to this post.