Occasional Contributor
Super ContributorIt may not be a bug. Pro follows the IEEE rules for HDL languages much more strictly than Standard. This could be one of those instances.
Occasional ContributorI don't think that's the case here. The IEEE VHDL93 standard says that in an ambiguous case (when it's not clear which overloaded function applies) it's considered an error. (But the above error is about OTHERS used with an unconstrained array type).
In my case, however, it is clear which function applies.
Also, I'm sure the order of the functions' definitions shouldn't determine which one applies. But it does. It seems that the most recently defined function is always the one that is applied. If I change the order of the definitions of the two from_my_bool_a functions, everything works fine.
I think this can be a really nasty thing in development. This behaviour can cause an FPGA implementation to behave differently than a RTL simulation or ASIC implementation.
