Forum Discussion
c-thaler
Occasional Contributor
1 year agoI now use the following workaround:
I defined an additional signal with the same type as the module output port.
The conversion is then done in a separate assignment outside of the entity instantiation.
architecture RTL of top_level is signal sig_out_b : my_bool_at(port_width-1 downto 0); begin U_MODULE: entity work.module generic map ( port_width => port_width ) port map ( in_a(0) => a, --from_my_bool_a(out_b) => b out_b => sig_out_b ); b <= from_my_bool_a(sig_out_b); end architecture;
Now Quartus selects the correct function.