Writing a host application that does not need to reprogram the FPGA

HRZ, thank you! I have been looking for this solution for about a month now... Doing what you mentioned worked perfectly. I am working with Quartus Prime 18.0 and a polite WARNING came up saying "CL_CONTEXT_COMPILER_MODE_ALTERA" is deprecated, please use "CL_CONTEXT_COMPILER_MODE_INTELFPGA". Either way it worked, but using the new variable name removed the warning.

Also for future readers, thanks to HRZ, I finally ran into this: https://www.altera.com/documentation/ewa1404851957878.html#ewa1405368788074 . It is the troubleshooting section of the Stratix V OpenCL porting guide. It lists environment variables and their functionality including this environment variable. From that page:

CL_CONTEXT_COMPILER_MODE_INTELFPGA

Unset this variable or set it to a value of 3. The OpenCL™ host runtime reprograms the FPGA as needed, which it does at least once during initialization. To prevent the host application from programming the FPGA, set this variable to a value of 3.

Important: When setting CL_CONTEXT_COMPILER_MODE_INTELFPGA, only use a value of 3.

Life saver. Thanks again.