working with the pin planner

Hi, this is my first post here and I'm as new and bloody to FPGA's. Please, don't get too angry with me asking probably obvious things, or perhaps in the wrong part of the forum (smile).

On an EBV SoCrates FPGA board, I'm trying to get some LEDs to blink. I'm trying as described here for a different board: http://zhehaomao.com/blog/fpga/2013/12/22/sockit-1.html

I wrote the Verilog files blinker.v and delay_ctrl.v and renamed sockit_test.v to led01.v (code below). Since my board does not have any keys, I tried to leave out the keys which still may contain certain bugs. My big issue, I'd like to ask here, is the pin planning.

To convert the described pin settings to my board, I found the following in my data sheets:

"Eight USER LEDs are connected to Signals of IOBANK4A. These Signals are connected to P13 in parallel."

then a table: "User LED FPGA Connection"

Function

Pin

FPGA Pin

LED0

IOB4A0

AH7

LED1

IOB4A4

AH9

LED2

IOB4A8

AF13

LED3

IOB4A12

AG14

LED4

IOB4A16

AH16

LED5

IOB4A20

AH18

LED6

IOB4A24

AG21

LED7

IOB4A28

AE22

as also, since I need a 50 MHz clock, I found:

"The clocking scheme of the 'SoCrates Evaluation Board' is build around an IDT EEPROM programmable clock generator 5V49EE904. This device has two clock sources and 9 programmable outputs. [...]"

Function

FPGA Pin

50MHz

Y13

50MHz

Y15

50MHz

V11

50MHz

V12

Ok, with that information, I just tried to work on the Pin planner. Initially I had some panel to edit "Function" and "Location". I entered pin name, pin location (table), and tried to run "I/O Assignment Analysis". The result were some errors. I worked on the Verilog files (trailing commas, etc.), untill finally some errors remained. I tried several options, and finally I somehow closed the panel to enter Function / Location of the pins. I thought it was just the properties panel, or early Pin Assignment, or the pin migration window, or the resources... my favorite was "early pin assignment", but they all looked different, though, to the initial editor panel. I closed the Pin Planner, even closed Quartus, and even the Virtual Box where I installed everything (Quartus 2, web edition, BTW). Nothing, when I (re)open the project, the pin planner does not offer anymore this initial window / option. How to get me my Pin Editor back again?

I tried to overcome the issue, by clicking on the location in the graphical representation of the chip (Cyclone V / 5CSXFC6C6U23C8ES should be the correct one), and editing the Properties. Now running the "I/O Assignment Analysis" I still get the following:

"pin AH9 does not support I/O standard 2.5-v pcml for LED[1]", and further errors such as "I/O pin LED[1] with termination logic option setting OCT 100 Ohms cannot be placed inside I/O Bank 4A because the I/O bank does not support the requested termination" - the same for AF13 and LED[2], what am I doing wrong here? What is the Pin Planner trying to tell me in "simple English"?

Further, for all LED pins I obtain also some warnings, such as "Reserve pin assignment ignored because of existing pin with name LED[0]", LED[1], 2 or 3. What am I doing wrong here?

Please can you help me to understand the error messages of the pin planner? In case, what can/may I do to further investigate and finally figure out what I am doing wrong here?

My code files look as follows:

// blinker.v
module blinker (
    input clk,
    input  delay,
    output reg  led,
    input reset
);
reg  count = 24'b0;
reg  pos = 3'b000;
reg running = 1'b1;
always @(pos) begin
    case (pos)
        3'b000: led <= 4'b0001;
        3'b001: led <= 4'b0010;
        3'b010: led <= 4'b0100;
        3'b011: led <= 4'b1000;
        3'b100: led <= 4'b0100;
        3'b101: led <= 4'b0010;
        default: led <= 4'b0000;
    endcase
end
always @(posedge clk) begin
    if (reset) begin
        count <= 24'b0;
        pos <= 3'b000;
        running <= 1'b1;
    end else if (running) begin // TODO check if necessary..
        if (count == 24'b0) begin
            count <= {delay, 20'b0};
            if (pos == 3'b101)
                pos <= 3'b000;
            else
                pos <= pos + 1'b1;
        end else begin
            count <= count - 1'b1;
        end
    end
end
endmodule

// delay_ctrl.v
module delay_ctrl (
    input clk,
    output  delay,
    input reset
);
reg  delay_intern = 4'b1000;
assign delay = delay_intern;
// TODO check if this is removed entirely
always @(posedge clk) begin
    if (reset)
        delay_intern <= 4'b1000;
end
endmodule

// led01.v - the top-level entity
module led01 (
    input CLOCK_50,
    output  LED
);
wire  delay;
wire main_clk = CLOCK_50;
delay_ctrl dc (
    .clk (main_clk),
    .delay (delay)
);
blinker b (
    .clk (main_clk),
    .delay (delay),
    .led (LED)
);

Thank you very much, in advance!!