Wireless Transmission using Cyclone II FPGA (Verilog HDL)

First some things that I do not understand from your design:

1) I do not understand why you are using this fifo for this project.

2) When all 4 bits of from_expansion are "0" you are emptying the fifo with reads.

3) On every "clk" clock cycle, when "from_expansion" is different from zero you will read in a new "from_expansion" in your fifo. In my opinion this can give rise to two problems:

1. When the data from your RF receiver last longer than the amount of words in your fifo, the fifo will be full. This gets unnoticed in your design.

2. What happens when you have transitions in your "from_expansion" signal between one state and the other? For example a change from: "1011" to "1100" could for example go over a number of clock cycles from "1011" to "1001" to "1101" to "1100". If such transitions from your 433 MHz receiver take longer than the clock period of your design, then they are all registered as separate values.

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Once a key is pressed, sometimes the MSB will be received first.

Sometimes, the LSB will be received first.

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Do you take into account the "full" and "empty" signals in your design. Whenever your fifo gets full, it will not read new data. So this could explain the strange behavior.

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And, only second time of the key press will trigger the LEDs to change.

Why is it so?

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This is probably caused by the length of your fifo.

If I don't use FIFO at the receiver side

then what should I add in to make it works?

what about another coding I have posted up?

sickmuse...

can you sent me a link for example design of wireless transmission using rf