Forum Discussion
Altera_Forum
Honored Contributor
16 years agoFirst some things that I do not understand from your design:
1) I do not understand why you are using this fifo for this project. 2) When all 4 bits of from_expansion are "0" you are emptying the fifo with reads. 3) On every "clk" clock cycle, when "from_expansion" is different from zero you will read in a new "from_expansion" in your fifo. In my opinion this can give rise to two problems:- When the data from your RF receiver last longer than the amount of words in your fifo, the fifo will be full. This gets unnoticed in your design.
- What happens when you have transitions in your "from_expansion" signal between one state and the other? For example a change from: "1011" to "1100" could for example go over a number of clock cycles from "1011" to "1001" to "1101" to "1100". If such transitions from your 433 MHz receiver take longer than the clock period of your design, then they are all registered as separate values.