wire Verilog to VHDL

This should do it:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
    PORT (
        inclk0 : IN std_logic
        );
END ENTITY test;
ARCHITECTURE rtl OF test IS
    SIGNAL sub_wire0 : std_logic_vector(4 DOWNTO 0);
    SIGNAL sub_wire5 : std_logic := '0';
    SIGNAL sub_wire2 : std_logic_vector(0 DOWNTO 0);
    SIGNAL sub_wire1 : std_logic_vector(1 DOWNTO 1);
    SIGNAL c1        : std_logic;
    SIGNAL c0        : std_logic;
    SIGNAL sub_wire3 : std_logic;
    SIGNAL sub_wire4 : std_logic_vector(1 DOWNTO 0);
    
BEGIN  -- ARCHITECTURE rtl
    sub_wire2(0) <= sub_wire0(0);
    sub_wire1(1) <= sub_wire0(1);
    c1 <= sub_wire1(1);
    c0 <= sub_wire2(0);
    sub_wire3 <= inclk0;
    sub_wire4 <= sub_wire5 & sub_wire3;
END ARCHITECTURE rtl;

after a quick glance this looks correct

Is there any tool to convert from verilog to vhdl.

vasireddyrajesh3 (http://www.alteraforum.com/forum/member.php?u=56700): Yes, X-HDL is a tool, but it wont work for files over 1024 bytes :mad:

schmalisch (http://www.alteraforum.com/forum/member.php?u=1078): Thank you for your help :)

Thank you for the info.