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Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
Icon for Contributor rankContributor
1 year ago

Windows sees USB blaster but Quartus doesn't, why?

After using my USB blaster successfully with SignalTap to configure and debug my Cyclone4 part, SignalTap and the programming software aren't reliably seeing the USB blaster (by which I mean only 5% ...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
I observed JTAG signal integrity issues, mainly related to TCK, with some customs designed boards.
Two issues have been identified:

- TCK line can pick up interfering signals, specifically clock signals with fast edges. Utimately, a TCK buffer need to be added.
- on small boards with short TCK line, ringing TCK edges caused false JTAG clocking. Could be fixed by adding a small load capacitor (10 to 22 pF near FPGA)

ASMI IP producing continuous DCLK has been found a popular interference source. Solution is to gate DCLK.

Regards
Frank