Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow?

So, as for the LEC tools, could you please provide an example when LEC can help (catch some bugs) while other tools are useless?

As for the FPGA flow, are LEC tools just involved in the RTL vs Netlist compare? What about verification of the mapped design (Netlist vs ma)?

Is there a post-mapped Netlist in FPGA (including timing information of the mapped design)?

How do I extract Pre-Mapped and Post-Mapped Netlists from Quartus?