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JJohn10's avatar
JJohn10
Icon for New Contributor rankNew Contributor
7 years ago

Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow?

Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow? There is no a P&R stage (as in ASIC flow)... Is it not enough just to check the logs and reports of the synthesis tools in order to...
Tricky's avatar
Tricky
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

FPGAs do have P&R flows. All the cells are in fixed locations, but it needs to map the synthesised netlist to these cells and work out the routing between them.

So the synthesised netlist will have no routing information. A routed design doesnt necessarily meet timing.

Full FPGAs often struggle in timing where in an ASIC it may have more freedom in the layout and routing.