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JDlug's avatar
JDlug
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5 years ago

Why is the build time of a simple project in Quartus Prime Pro so long?

Hello, For a very simple project, compilation process in "Quartus Prime Pro" for "Stratix 10" lasts about 10 minutes, while a compilation of the same project for "MAX 10" in Quartus Standard Edition...
SyafieqS's avatar
SyafieqS
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5 years ago

Hi Jacek,

Generally, there many ways you can change manually in order to speed the compilation process. Refer to link below for details. Document below shows configurations and steps depending on your need. Easily way for setting if you dont want to manually change it is to enable Aggressive Compile Time (Reduces the compile time required to implement the design with reduced effort and fewer performance optimizations). Go to Assignment --> Setting --> Compiler setting --> Optimization mode --> select (desired optimization mode,refer to link below for type of opt mode). Hopefully it helps.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-compiler.pdf

p60- Optimization mode

p84- Reducing compilation time

Thanks,

Regards

JDlug's avatar
JDlug
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5 years ago
Hi again, I studied the document from the link. I checked I think all promising options. I got no positive results. :( Even very very tiny VHDL project, I tested this time, takes me 9 minutes to build. This may not be a problem for large projects, but I often have to check many versions of different small parts of large designs and then it becomes very frustrating. These 9 minutes look like a tribute that I always have to pay for every use of Quartus Primne Pro. Quartus Prime Standard Edition takes seconds for the same project. What is the reason? Is it because of Stratix 10? I would be grateful for an explanation. I use Intel Core i9-9900K CPU @ 3.6GHz with 64GB RAM and SSD. and I of course have added: "set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL" to the project. Here is the simplest design that I used for testing this time: ................................................. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY e1 IS PORT ( led : inout std_logic ); END e1; ARCHITECTURE arch1 OF e1 IS BEGIN led <='1'; END arch1; ................................................. and here are my Quartus settings in QSF file modified after reading the document from the link: ................................................. set_global_assignment -name FAMILY "Stratix 10" set_global_assignment -name DEVICE 1SX280HU2F50E1VG set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE COMPILE TIME" set_global_assignment -name FAST_PRESERVE AUTO -entity e1 set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Pro Edition" set_global_assignment -name TOP_LEVEL_ENTITY e1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_location_assignment PIN_AH32 -to led set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to led -entity e1 set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS ON set_global_assignment -name PHYSICAL_SYNTHESIS OFF set_global_assignment -name ALLOW_REGISTER_RETIMING OFF set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION off -entity e1 set_global_assignment -name FRACTAL_SYNTHESIS OFF -entity e1 ................................................. Can you tell me what else to add here to eliminate this strange Quartus behavior? Thanks, (jd)