It’s not necessary for both the DAT and DRT to occur before the latch edge.
Essentially, we focus on the setup/hold slack, which depends on the both the Data Arrival Path (DAT) and the Data Required Path (DRT). For setup, the DAT must be > DRT. For Hold, DRT > DAT.
For further details, you can check out this YouTube video:
https://www.youtube.com/watch?v=6D-w8mOttnE
We also have a video series on Timing Analyzer.
https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Additionally, TimeQuest User Guide:
https://web02.gonzaga.edu/faculty/talarico/CP430/LEC/TimeQuest_User_Guide.pdf
Regards,
Richard Tan
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