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Altera_Forum's avatar
Altera_Forum
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13 years ago

why add this code will got loop and compile running like stop

signal enableit : STD_LOGIC;
signal wholelooptrue : STD_LOGIC = '1';
enableit <= '1';
process(CLOCK_50)
    VARIABLE last_clk : std_logic := '0';
    VARIABLE counter : integer := 0;
    VARIABLE last_counter : integer := 0;
    
    begin
    while (whilelooptrue = enableit) loop
    
        if SW(0) = '1' then
            enableit <= '1';
            if (CLOCK_50 = '0') AND (last_clk = '1') then
                
                if (counter = 0) then
                    txdata8 <= preamble;
                end if;
                if (counter = 1) then
                    txdata8 <= preamble;
                end if;
                if (counter = 2) then
                    txdata8 <= preamble;
                end if;
                if (counter = 3) then
                    txdata8 <= preamble; --end
                end if;
                if (counter = 4) then
                    txdata8 <= preamble;
                end if;
                if (counter = 5) then
                    txdata8 <= preamble;
                end if;
                if (counter = 6) then
                    txdata8 <= preamble;
                end if;
                if (counter = 7) then
                    txdata8 <= SFD;
                end if;
                if (counter = 8) then
                    txdata8 <= dest_mac_addr1;
                end if;
                if (counter = 9) then
                    txdata8 <= dest_mac_addr2;
                end if;
                if (counter = 10) then
                    txdata8 <= dest_mac_addr3;
                end if;
                if (counter = 11) then
                    txdata8 <= dest_mac_addr4;
                end if;
                if (counter = 12) then
                    txdata8 <= dest_mac_addr5;
                end if;
                if (counter = 13) then
                    txdata8 <= dest_mac_addr6;
                end if;
                if (counter = 14) then
                    txdata8 <= src_mac_addr1;
                end if;
                if (counter = 15) then
                    txdata8 <= src_mac_addr2;
                end if;
                if (counter = 16) then
                    txdata8 <= src_mac_addr3;
                end if;
                if (counter = 17) then
                    txdata8 <= src_mac_addr4;
                end if;
                if (counter = 18) then
                    txdata8 <= src_mac_addr5;
                end if;
                if (counter = 19) then
                    txdata8 <= src_mac_addr6;
                end if;
                if (counter = 20) then
                    txdata8 <= wholepacketlength1;
                end if;            
                if (counter = 21) then
                    txdata8 <= wholepacketlength2;
                end if;            
                if (counter = 22) then
                    txdata8 <= payload;
                end if;            
                if (counter = 23) then
                    txdata8 <= emptyhex;
                end if;            
                if (counter = 24) then
                    txdata8 <= X"10";--CheckSumResult;
                end if;
                
                last_counter := counter;
                counter := counter + 1;
            end if;
            
            if (CLOCK_50 = '1') AND (last_clk = '0') then
                if (counter >= 25) then
                    enableit <= '0';
                end if;
            end if;
        else
            enableit <= '0';
        end if;
    end loop;
    last_clk := CLOCK_50;
    end process;

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Probably because in some cases (sw(0) not '1') your while loop is an infinite loop.

    This will not synthesize properly, it doesn't represent proper hardware. The process is executed at each clock edge, so you don't need the while loop. Just start your process with a if rising_edge(clock_50) and do everything inside the if block.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    The process is executed at each clock edge.

    --- Quote End ---

    No. It's no proper synchronous code at all, because there's no edge sensitive event expression.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    if rising_edge(clock_50) is good

    however i would like to use switch on to start this process
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    you should read the switch signal value inside the clocked part of your process so that you only start doing something when the switch is pressed.