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Altera_Forum's avatar
Altera_Forum
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12 years ago

why add this code will got loop and compile running like stop

signal enableit : STD_LOGIC; signal wholelooptrue : STD_LOGIC = '1'; enableit <= '1'; process(CLOCK_50) VARIABLE last_clk : std_logic := '0'; VARIABLE counter : integer := 0; VARIABLE l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Probably because in some cases (sw(0) not '1') your while loop is an infinite loop.

This will not synthesize properly, it doesn't represent proper hardware. The process is executed at each clock edge, so you don't need the while loop. Just start your process with a if rising_edge(clock_50) and do everything inside the if block.