Altera_Forum
Honored Contributor
Honored Contributorwhy add this code will got loop and compile running like stop
signal enableit : STD_LOGIC;
signal wholelooptrue : STD_LOGIC = '1';
enableit <= '1';
process(CLOCK_50)
VARIABLE last_clk : std_logic := '0';
VARIABLE counter : integer := 0;
VARIABLE l...
